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An Efficient OpenCL-Based Implementation of a SHA-3 Co-Processor on an FPGA-Centric Platform.
Hachem Bensalem
Yves Blaquière
Yvon Savaria
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2023)
Keyphrases
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digital signal
real time
parallel architecture
layered architecture
reconfigurable hardware
high speed
graphics processing units
computing platform
platform independent
secure information sharing
hardware implementation
shared memory
hardware architecture
instruction set
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