Sub-ps resolution programmable delays implemented in a Xilinx FPGA.
Safa BerrimaYves BlaquièreYvon SavariaPublished in: MWSCAS (2017)
Keyphrases
- pipelined architecture
- fpga device
- hardware implementation
- field programmable gate array
- high speed
- low cost
- fpga implementation
- hardware architecture
- single chip
- digital signal processors
- general purpose
- dedicated hardware
- evolutionary algorithm
- programmable logic
- signal processing
- reconfigurable hardware
- general purpose processors
- hardware description language
- low resolution
- parallel computing
- database
- high resolution
- multiresolution
- artificial neural networks
- pattern recognition
- multiscale
- image sequences
- image processing
- machine learning
- neural network