A 237 Gbps Unrolled Hardware Polar Decoder.
Pascal GiardGabi SarkisClaude ThibeaultWarren J. GrossPublished in: CoRR (2014)
Keyphrases
- low cost
- fpga implementation
- hardware implementation
- real time
- low complexity
- hardware architecture
- hardware and software
- motion estimation
- frequency domain
- rotation invariant
- computing systems
- computing power
- computer systems
- error control
- hardware design
- error detection
- xilinx virtex
- personal computer
- data acquisition
- parallel hardware
- successive approximation
- image processing
- vlsi implementation
- polar coordinates
- fourier transform
- feature vectors