A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs.
Pascal GiardGabi SarkisClaude ThibeaultWarren J. GrossPublished in: SiPS (2015)
Keyphrases
- low complexity
- vlsi architecture
- high data rate
- distributed video coding
- distributed source coding
- computational complexity
- motion estimation
- rate allocation
- video encoding
- multiple description coding
- video coding scheme
- bit plane
- lower complexity
- real time
- decoding complexity
- video encoder
- wyner ziv
- field programmable gate array
- frequency domain
- mode decision
- video streaming