Paolo Meloni

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 53

Top Topics

Automated Design

Reconfigurable Architecture

Top Venues

Publications

Matteo Antonio Scrugli, Gianluca Leone, Paola Busia, Paolo Meloni
sEMG-Based Gesture Recognition with Spiking Neural Networks on Low-Power FPGA. DASIP (2024)
Paola Busia, Andrea Cossettini, Thorir Mar Ingolfsson, Simone Benatti, Alessio Burrello, Victor J. B. Jung, Moritz Scherer, Matteo Antonio Scrugli, Adriano Bernini, Pauline Ducouret, Philippe Ryvlin, Paolo Meloni, Luca Benini
Reducing False Alarms in Wearable Seizure Detection With EEGformer: A Compact Transformer Model for MCUs. IEEE Trans. Biomed. Circuits Syst. 18 (3) (2024)
Paola Busia, Matteo Antonio Scrugli, Victor Jean-Baptiste Jung, Luca Benini, Paolo Meloni
A Noisy Beat is Worth 16 Words: a Tiny Transformer for Low-Power Arrhythmia Classification on Microcontrollers. CoRR (2024)
Paola Busia, Claudio Marche, Paolo Meloni, Diego Reforgiato Recupero
Design of an AI-driven Architecture with Cobots for Digital Transformation to Enhance Quality Control in the Food Industry. UMAP (Adjunct Publication) (2024)
Paolo Meloni, Paola Busia, Gianluca Leone, Luca Martis, Matteo Antonio Scrugli
Exploiting FPGAs and Spiking Neural Networks at the Micro-Edge: The EdgeAI Approach. ARC (2024)
Matteo Antonio Scrugli, Paola Busia, Gianluca Leone, Paolo Meloni
On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis. DATE (2024)
Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni
Spiking Neural Networks for Integrated Reach-to-Grasp Decoding on FPGAs. BioCAS (2023)
Matteo Antonio Scrugli, Bojan Blazica, Luigi Raffo, Paolo Meloni
A Microcontroller-Based Platform for Cognitive Tracking of Sensorimotor Training. IEEE Access 11 (2023)
Francesco Ratto, Ángela Porras Máinez, Carlo Sau, Paolo Meloni, Gianfranco Deriu, Stefano Delucchi, Massimo Massa, Luigi Raffo, Francesca Palumbo
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators. J. Signal Process. Syst. 95 (9) (2023)
Gianluca Leone, Luigi Raffo, Paolo Meloni
On-FPGA Spiking Neural Networks for End-to-End Neural Decoding. IEEE Access 11 (2023)
Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. ARC (2023)
Gianluca Leone, Luigi Raffo, Paolo Meloni
A Bandwidth-Efficient Emulator of Biologically-Relevant Spiking Neural Networks on FPGA. IEEE Access 10 (2022)
Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
An Adaptive Cognitive Sensor Node for ECG Monitoring in the Internet of Medical Things. IEEE Access 10 (2022)
Paola Busia, Gianfranco Deriu, Luca Rinelli, Cristina Chesta, Luigi Raffo, Paolo Meloni
Target-Aware Neural Architecture Search and Deployment for Keyword Spotting. IEEE Access 10 (2022)
Matteo Antonio Scrugli, Bojan Blazica, Paolo Meloni
An adaptable cognitive microcontroller node for fitness activity recognition. CoRR (2022)
Paola Busia, Andrea Cossettini, Thorir Mar Ingolfsson, Simone Benatti, Alessio Burrello, Moritz Scherer, Matteo Antonio Scrugli, Paolo Meloni, Luca Benini
EEGformer: Transformer-Based Epilepsy Detection on Raw EEG Traces for Low-Channel-Count Wearable Continuous Monitoring Devices. BioCAS (2022)
Paola Busia, Ilias Theodorakopoulos, Vasileios K. Pothos, Nikos Fragoulis, Paolo Meloni
Dynamic Pruning for Parsimonious CNN Inference on Embedded Systems. DASIP (2022)
Matteo Antonio Scrugli, Bojan Blazica, Paolo Meloni
An Adaptable Cognitive Microcontroller Node for Fitness Activity Recognition. DASIP (2022)
Paolo Meloni, Alessandro Serpi
Integration of Energy Storage Systems within Modular Multilevel Converters for Medium-Voltage Distribution Networks. IECON (2022)
Georg Buchgeher, Gerald Czech, Adriano Souza Ribeiro, Werner Kloihofer, Paolo Meloni, Paola Busia, Gianfranco Deriu, Maura Pintor, Battista Biggio, Cristina Chesta, Luca Rinelli, David Solans, Manuel Portela
Task-Specific Automation in Deep Learning Processes. DEXA Workshops (2021)
Paola Busia, Svetlana Minakova, Todor P. Stefanov, Luigi Raffo, Paolo Meloni
ALOHA: A Unified Platform-Aware Evaluation Method for CNNs Execution on Heterogeneous Systems at the Edge. IEEE Access 9 (2021)
Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
An adaptive cognitive sensor node for ECG monitoring in the Internet of Medical Things. CoRR (2021)
Frank Hannig, Paolo Meloni, Matteo Spallanzani, Matthias Ziegler
Proceedings of the DATE Friday Workshop on System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA 2021). CoRR (2021)
S. Loddo, M. Soccol, A. Perra, M. Ucchesu, Paolo Meloni, Massimo Barbaro, M. Lo Cascio, C. Sirca
Biosensing IoT Platform for Water Management in Vineyards. ISCAS (2020)
Marco Carreras, Gianfranco Deriu, Luigi Raffo, Luca Benini, Paolo Meloni
Optimizing Temporal Convolutional Network inference on FPGA-based accelerators. CoRR (2020)
Gianluca Leone, Luigi Raffo, Paolo Meloni
ZyON: Enabling Spike Sorting on APSoC-Based Signal Processors for High-Density Microelectrode Arrays. IEEE Access 8 (2020)
Paolo Meloni, Daniela Loi, Gianfranco Deriu, Marco Carreras, Francesco Conti, Alessandro Capotondi, Davide Rossi
Exploring NEURAghe: A Customizable Template for APSoC-Based CNN Inference at the Edge. IEEE Embed. Syst. Lett. 12 (2) (2020)
Marco Carreras, Gianfranco Deriu, Luigi Raffo, Luca Benini, Paolo Meloni
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Marco Carreras, Gianfranco Deriu, Paolo Meloni
Flexible Acceleration of Convolutions on FPGAs: NEURAghe 2.0. CPS Summer School, PhD Workshop (2019)
Paolo Meloni, Antonio Garufi, Gianfranco Deriu, Marco Carreras, Daniela Loi
CNN hardware acceleration on a low-power and low-cost APSoC. DASIP (2019)
Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
Runtime-Adaptive Cognitive IoT Nodes. CPS Summer School, PhD Workshop (2019)
Sara Zaher, Davide Lonardoni, Fabio Boi, Giovanni Pietro Seu, Gian Nicola Angotzi, Paolo Meloni, Luca Berdondini
A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties. NER (2019)
Matteo Antonio Scrugli, Daniela Loi, Luigi Raffo, Paolo Meloni
A runtime-adaptive cognitive IoT node for healthcare monitoring. CF (2019)
Paolo Meloni, Daniela Loi, Paola Busia, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Todor P. Stefanov, Svetlana Minakova, Francesco Conti, Luca Benini, Maura Pintor, Battista Biggio, Bernhard Moser, Natalia Shepeleva, Nikos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
Optimization and deployment of CNNs at the edge: the ALOHA experience. CF (2019)
Giovanni Pietro Seu, Gian Nicola Angotzi, Fabio Boi, Luigi Raffo, Luca Berdondini, Paolo Meloni
Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays. IEEE Trans. Biomed. Circuits Syst. 12 (4) (2018)
Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Maura Pintor, Battista Biggio, Oscar Ripolles, David Solans, Francesco Conti, Luca Benini, Todor P. Stefanov, Svetlana Minakova, Bernhard Moser, Natalia Shepeleva, Michael Masin, Francesca Palumbo, Nikos Fragoulis, Ilias Theodorakopoulos
Architecture-aware design and implementation of CNN algorithms for embedded inference: the ALOHA project. ICM (2018)
Paolo Meloni, Daniela Loi, Gianfranco Deriu, Andy D. Pimentel, Dolly Sapra, Bernhard Moser, Natalia Shepeleva, Francesco Conti, Luca Benini, Oscar Ripolles, David Solans, Maura Pintor, Battista Biggio, Todor P. Stefanov, Svetlana Minakova, Nikolaos Fragoulis, Ilias Theodorakopoulos, Michael Masin, Francesca Palumbo
ALOHA: an architectural-aware framework for deep learning at the edge. INTESA@ESWEEK (2018)
Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Giovanni Pietro Seu, Gian Nicola Angotzi, Giuseppe Tuveri, Luigi Raffo, Luca Berdondini, Alessandro Maccione, Paolo Meloni
On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration. IPDPS Workshops (2017)
Francesca Palumbo, Carlo Sau, Danilo Pani, Paolo Meloni, Luigi Raffo
Feasibility Study of Real-Time Spiking Neural Network Simulations on a Swarm Intelligence Based Digital Architecture. IPDPS Workshops (2017)
Paolo Meloni, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo
Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs. J. Syst. Archit. 76 (2017)
Francesca Palumbo, Tiziana Fanni, Carlo Sau, Paolo Meloni
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy. J. Signal Process. Syst. 87 (1) (2017)
Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. CoRR (2017)
Carlo Sau, Francesca Palumbo, Maxime Pelcat, Julien Heulot, Erwan Nogues, Daniel Ménard, Paolo Meloni, Luigi Raffo
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing. IEEE Embed. Syst. Lett. 9 (3) (2017)
Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. 85 (1) (2016)
Paolo Meloni, Francesca Palumbo, Claudio Rubattu, Giuseppe Tuveri, Danilo Pani, Luigi Raffo
MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation. Microprocess. Microsystems 43 (2016)
Carlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo, Maxime Pelcat, Francesca Palumbo
Demo: Reconfigurable Platform Composer Tool. DASIP (2016)
Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo
Power and clock gating modelling in coarse grained reconfigurable systems. Conf. Computing Frontiers (2016)
Francesca Palumbo, Carlo Sau, Tiziana Fanni, Paolo Meloni, Luigi Raffo
Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms. SiPS (2016)
Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti, Luigi Raffo
On-the-fly adaptivity for process networks over shared-memory platforms. Microprocess. Microsystems 46 (2016)
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
Curbing the roofline: a scalable and flexible architecture for CNNs on FPGA. Conf. Computing Frontiers (2016)
Francesca Palumbo, Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo
Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures. J. Electr. Comput. Eng. 2016 (2016)
Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, Luca Benini
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC. ReConFig (2016)
Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo
Power modelling for saving strategies in coarse grained reconfigurable systems. ReConFig (2015)
Carlo Sau, Luca Fanni, Paolo Meloni, Luigi Raffo, Francesca Palumbo
Reconfigurable coprocessors synthesis in the MPEG-RVC domain. ReConFig (2015)
Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. DASIP (2015)
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks. MES (2014)
Francesca Palumbo, Nicola Carta, Danilo Pani, Paolo Meloni, Luigi Raffo
The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. J. Real Time Image Process. 9 (1) (2014)
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Igor Loi, Francesco Conti
Online process transformation for polyhedral process networks in shared-memory MPSoCs. MECO (2014)
Nicola Carta, Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo
A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (2) (2014)
Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, Giuseppe Notarangelo
ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems 37 (8-C) (2013)
Giuseppe Tuveri, Simone Secchi, Paolo Meloni, Luigi Raffo, Emanuele Cannella
A runtime adaptive H.264 video-decoding MPSoC platform. DASIP (2013)
Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Giuseppe Tuveri
A Low Overhead Self-adaptation Technique for KPN Applications on NoC-based MPSoCs. PECCS (2013)
Onur Derin, Emanuele Cannella, Giuseppe Tuveri, Paolo Meloni, Todor P. Stefanov, Leandro Fiorin, Luigi Raffo, Mariagiovanna Sami
A system-level approach to adaptivity and fault-tolerance in NoC-based MPSoCs: The MADNESS project. Microprocess. Microsystems 37 (6-7) (2013)
Paolo Meloni, Christophe Jégo
Welcome to the 2013 conference on design and architectures for signal and image processing (DASIP) in Cagliari, Italy. DASIP (2013)
Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer
Exploiting binary translation for fast ASIP design space exploration on FPGAs. DATE (2012)
Paolo Meloni, Sebastiano Pomata, Luigi Raffo, Roberta Piscitelli, Andy D. Pimentel
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems. ICSAMOS (2012)
Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo
ASAM: Automatic Architecture Synthesis and Application Mapping. DSD (2012)
Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, Todor P. Stefanov
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks. VLSI Design 2012 (2012)
Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer
Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. VLSI Design 2012 (2012)
Onur Derin, Prasanth Kuncheerath Ramankutty, Paolo Meloni, Emanuele Cannella
Towards Self-Adaptive KPN Applications on NoC-Based MPSoCs. Adv. Softw. Eng. 2012 (2012)
Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Emanuele Cannella, Todor P. Stefanov, Onur Derin, Leandro Fiorin, Mariagiovanna Sami
System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project Approach. DSD (2012)
Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Meloni, Olaf Neugebauer, Andy D. Pimentel
Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not? ESTIMedia (2011)
Paolo Meloni, Simone Secchi, Luigi Raffo
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. IEEE Embed. Syst. Lett. 2 (1) (2010)
Paolo Meloni, Simone Secchi, Luigi Raffo
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC (2010)
Simone Secchi, Paolo Meloni, Luigi Raffo
Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. ISPASS (2010)
Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
NoC Design and Implementation in 65nm Technology. NOCS (2007)
Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini
Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007 (2007)
Paolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo
On the impact of serialization on the cache performances in Network-on-Chip based MPSoCs. DSD (2007)
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15 (8) (2007)
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
Designing Routing and Message-Dependent Deadlock Free Networks on Chips. VLSI-SoC (Selected Papers) (2006)
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
Designing application-specific networks on chips with floorplan information. ICCAD (2006)
Paolo Meloni, Salvatore Carta, Roberto Argiolas, Luigi Raffo, Federico Angiolini
Area and Power Modeling Methodologies for Networks-on-Chip. Nano-Net (2006)
Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC (2006)
Paolo Meloni, Srinivasan Murali, Salvatore Carta, Massimo Camplani, Luigi Raffo, Giovanni De Micheli
Routing Aware Switch Hardware Customization for Networks on Chips. Nano-Net (2006)
Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
Contrasting a NoC and a traditional interconnect fabric with layout awareness. DATE (2006)
Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo
Networks on Chips: A Synthesis Perspective. PARCO (2005)