Simone Casale Brunet

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 25

Top Topics

Parallel Execution

Model Predictive Control

Design Space Exploration

High Level Synthesis

Top Venues

Publications

Simone Casale Brunet, Marco Mattavelli, Leonardo Chiariglione
Exploring the data of blockchain-based metaverses. MetaCom (2023)
Aurelien Bloch, Simone Casale Brunet, Marco Mattavelli
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms. MCSoC (2021)
Aurelien Bloch, Simone Casale Brunet, Marco Mattavelli
SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis. MCSoC (2021)
Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs. J. Signal Process. Syst. 92 (10) (2020)
Endri Bezati, Simone Casale Brunet, Romuald Mosqueron, Marco Mattavelli
An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms. ICASSP (2019)
Apostolos Modas, Simone Casale Brunet, Robert J. Stewart, Endri Bezati, Junaid Jameel Ahmad, Marco Mattavelli
Shared-variable Synchronization Approaches for Dynamic Data Flow Programs. SiPS (2018)
Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati
Towards in the Field Fast Pathogens Detection Using FPGAs. FPL (2018)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines. SiPS (2018)
Simone Casale Brunet, Marco Mattavelli
Execution Trace Graph of Dataflow Process Networks. IEEE Trans. Multi Scale Comput. Syst. 4 (3) (2018)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High level synthesis of Smith-Waterman dataflow implementations. ICASSP (2017)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs. ACSSC (2017)
Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms. EUSIPCO (2017)
Simone Casale Brunet, Endri Bezati, Aurelien Bloch, Marco Mattavelli
Profiling of dynamic dataflow programs on MPSoC multi-core architectures. ACSSC (2017)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Design space exploration of dataflow-based Smith-Waterman FPGA implementations. SiPS (2017)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Programming Models and Methods for Heterogeneous Parallel Embedded Systems. MCSoC (2016)
Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. 85 (1) (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High-Precision Performance Estimation of Dynamic Dataflow Programs. MCSoC (2016)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. SAMOS (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Trace-based manycore partitioning of stream-processing applications. ACSSC (2016)
Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Performance estimation of program partitions on multi-core platforms. PATMOS (2016)
Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies. J. Signal Process. Syst. 84 (3) (2016)
Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
A Partition Scheduler Model for Dynamic Dataflow Programs. ICCS (2016)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
High-level system synthesis and optimization of dataflow programs for MPSoCs. ACSSC (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. ICCS (2015)
Damien de Saint Jorre, Claudio Alberti, Marco Mattavelli, Simone Casale Brunet
Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms. ICIP (2014)
Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale
TURNUS: An open-source design space exploration framework for dynamic stream programs. DASIP (2014)
Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. SiPS (2014)
Jörn W. Janneck, Gustav Cedersjö, Endri Bezati, Simone Casale Brunet
Dataflow machines. ACSSC (2014)
Jörn W. Janneck, Simone Casale Brunet, Marco Mattavelli
Characterizing communication behavior of dataflow programs using trace analysis. ICSAMOS (2014)
Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. ICSAMOS (2014)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. DASIP (2014)
Ab Al-Hadi Ab Rahman, Simone Casale Brunet, Claudio Alberti, Marco Mattavelli
A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations. ICASSP (2014)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. ACSSC (2013)
Simone Casale Brunet, Marco Mattavelli, Claudio Alberti, Jörn W. Janneck
Representing Guard Dependencies in Dataflow Execution Traces. CICSyN (2013)
Simone Casale Brunet, Claudio Alberti, Marco Mattavelli, Jörn W. Janneck
Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem. ISPA (2013)
Simone Casale Brunet, Claudio Alberti, Marco Mattavelli, Jörn W. Janneck
Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems. DASIP (2013)
Ab Al-Hadi Ab Rahman, Simone Casale Brunet, Claudio Alberti, Marco Mattavelli
Dataflow program analysis and refactoring techniques for design space exploration: MPEG-4 AVC/H.264 decoder implementation case study. DASIP (2013)
Massimo Canale, Simone Casale Brunet
A Lego Mindstorms NXT experiment for Model Predictive Control education. ECC (2013)
Simone Casale Brunet, Abdallah Elguindy, Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck
Methods to explore design space for MPEG RMC codec specifications. Signal Process. Image Commun. 28 (10) (2013)
Simone Casale Brunet, Marco Mattavelli, Claudio Alberti, Jörn W. Janneck
Systems design space exploration by serial dataflow program execution. ACSSC (2013)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
Partitioning and optimization of high level stream applications for multi clock domain architectures. SiPS (2013)
Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
Buffer optimization based on critical path analysis of a dataflow program design. ISCAS (2013)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck, Jani Boutellier
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework. DASIP (2013)
Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
TURNUS: A design exploration framework for dataflow system design. ISCAS (2013)
Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
Profiling of Dataflow Programs Using Post Mortem Causation Traces. SiPS (2012)
Ab Al-Hadi Ab Rahman, Richard Thavot, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. DASIP (2012)