Endri Bezati

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 33

Top Topics

Design Space Exploration

Model Predictive Control

Top Venues

J. Signal Process. Syst.

Publications

Endri Bezati
ART: An Actor transition systems RunTime for enabling efficient partitioning of neural network graphs. CODAI (2023)
Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks. PACT (2022)
Endri Bezati, Mahyar Emami, Jörn W. Janneck, James R. Larus
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report). CoRR (2021)
Süleyman Savas, Endri Bezati, Jörn W. Janneck
Generating hardware and software for RISC-V cores generated with Rocket Chip generator. SoCC (2021)
Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems. FPGA (2021)
Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs. J. Signal Process. Syst. 92 (10) (2020)
Endri Bezati, Mahyar Emami, James R. Larus
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis. FPGA (2020)
Aurelien Bloch, Endri Bezati, Marco Mattavelli
Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis. SiPS (2020)
Gábor Paller, Endri Bezati, Nebojsa Tausan, Gabor Farkas, Gábor Élö
Dataflow-based Heterogeneous Code Generator for IoT Applications. MODELSWARD (2019)
Aurelien Bloch, Endri Bezati, Marco Mattavelli
Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism. ICCS (5) (2019)
Endri Bezati, Simone Casale Brunet, Romuald Mosqueron, Marco Mattavelli
An Heterogeneous Compiler of Dataflow Programs for Zynq Platforms. ICASSP (2019)
Apostolos Modas, Simone Casale Brunet, Robert J. Stewart, Endri Bezati, Junaid Jameel Ahmad, Marco Mattavelli
Shared-variable Synchronization Approaches for Dynamic Data Flow Programs. SiPS (2018)
Simone Casale Brunet, Thierry Schüpbach, Nicolas Guex, Christian Iseli, Alan Bridge, Dmitry Kuznetsov, Christian J. A. Sigrist, Phillippe Lemercier, Ioannis Xenarios, Endri Bezati
Towards in the Field Fast Pathogens Detection Using FPGAs. FPL (2018)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Anatoly Prihozhy, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines. SiPS (2018)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High level synthesis of Smith-Waterman dataflow implementations. ICASSP (2017)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs. ACSSC (2017)
Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms. EUSIPCO (2017)
Simone Casale Brunet, Endri Bezati, Aurelien Bloch, Marco Mattavelli
Profiling of dynamic dataflow programs on MPSoC multi-core architectures. ACSSC (2017)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Design space exploration of dataflow-based Smith-Waterman FPGA implementations. SiPS (2017)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Programming Models and Methods for Heterogeneous Parallel Embedded Systems. MCSoC (2016)
Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. J. Signal Process. Syst. 85 (1) (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
High-Precision Performance Estimation of Dynamic Dataflow Programs. MCSoC (2016)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms. SAMOS (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Trace-based manycore partitioning of stream-processing applications. ACSSC (2016)
Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Performance estimation of program partitions on multi-core platforms. PATMOS (2016)
Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies. J. Signal Process. Syst. 84 (3) (2016)
Malgorzata Michalska, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
A Partition Scheduler Model for Dynamic Dataflow Programs. ICCS (2016)
Malgorzata Michalska, Nicolas Zufferey, Endri Bezati, Marco Mattavelli
Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures. MCSoC (2016)
Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck
High-level system synthesis and optimization of dataflow programs for MPSoCs. ACSSC (2016)
Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs. ICCS (2015)
Anatoly Prihozhy, Endri Bezati, Ab Al-Hadi Ab Rahman, Marco Mattavelli
Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (10) (2015)
Simone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale
TURNUS: An open-source design space exploration framework for dynamic stream programs. DASIP (2014)
Massimo Canale, Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Jörn W. Janneck
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling. SiPS (2014)
Jörn W. Janneck, Gustav Cedersjö, Endri Bezati, Simone Casale Brunet
Dataflow machines. ACSSC (2014)
Carlo Sau, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case. ICSAMOS (2014)
Simone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control. DASIP (2014)
Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli
High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms. J. Real Time Image Process. 9 (1) (2014)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications. ACSSC (2013)
Endri Bezati, Ghislain Roquier, Marco Mattavelli
Live demonstration: High level software and hardware synthesis of dataflow programs. ISCAS (2013)
Simone Casale Brunet, Abdallah Elguindy, Endri Bezati, Richard Thavot, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck
Methods to explore design space for MPEG RMC codec specifications. Signal Process. Image Commun. 28 (10) (2013)
Endri Bezati, Marco Mattavelli, Jörn W. Janneck
High-level synthesis of dataflow programs for signal processing systems. ISPA (2013)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Marco Mattavelli, Edoardo Amaldi, Jörn W. Janneck
Partitioning and optimization of high level stream applications for multi clock domain architectures. SiPS (2013)
Simone Casale Brunet, Endri Bezati, Claudio Alberti, Ghislain Roquier, Marco Mattavelli, Jörn W. Janneck, Jani Boutellier
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework. DASIP (2013)
Ghislain Roquier, Endri Bezati, Marco Mattavelli
Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs. J. Electr. Comput. Eng. 2012 (2012)
Ab Al-Hadi Ab Rahman, Richard Thavot, Simone Casale Brunet, Endri Bezati, Marco Mattavelli
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. DASIP (2012)
Ghislain Roquier, Endri Bezati, Richard Thavot, Marco Mattavelli
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms. DASIP (2011)
Endri Bezati, Hervé Yviquel, Mickaël Raulet, Marco Mattavelli
A unified hardware/software co-synthesis solution for signal processing systems. DASIP (2011)
Endri Bezati, Marco Mattavelli, Mickaël Raulet
RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding. DASIP (2010)