Lech Józwiak

Publication Activity (10 Years)

Years Active: 1990-2023
Publications (10 Years): 9

Top Venues

Microprocess. Microsystems

MECO

DDECS

ASAP

Publications

Lech Józwiak, Francesco Leporati
. Microprocess. Microsystems 98 (2023)
Yahya Jan, Lech Józwiak
Quality-driven Design of Deep Neural Network Accelerators for CPS and IoT Applications. MECO (2021)
Tong Geng, Erkan Diken, Tianqi Wang, Lech Józwiak, Martin C. Herbordt
An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures. HPEC (2018)
Roel Jordans, Lech Józwiak, Henk Corporaal, Rosilde Corvino
Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project. Microprocess. Microsystems 51 (2017)
Lech Józwiak
Advanced mobile and wearable systems. Microprocess. Microsystems 50 (2017)
Radovan Stojanovic, Lech Józwiak
Special issue on cyber-physical systems. Microprocess. Microsystems 52 (2017)
Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
Message from the chairs. MECO (2016)
Francesco Leporati, Lech Józwiak
Special Section on European Projects in Embedded System Design 2015. Microprocess. Microsystems 47 (2016)
Lech Józwiak
Wearable and mobile systems. MECO (2016)
Erkan Diken, Martin J. O'Riordan, Roel Jordans, Lech Józwiak, Henk Corporaal, David Moloney
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths. ASAP (2015)
David Perlaza, Adam Postula, Lech Józwiak, Tadeusz A. Wysocki
FPGA-accelerated simulation engine for non-viral gene delivery. ICSPCS (2015)
Erkan Diken, Lech Józwiak
A compilation technique and performance profits for VLIW with heterogeneous vectors. MECO (2015)
Francesco Leporati, Lech Józwiak
MICPRO special issue on European projects in embedded system design 2014. Microprocess. Microsystems 39 (8) (2015)
Francesco Leporati, Lech Józwiak
Preface. Microprocess. Microsystems 38 (8) (2014)
Roel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal
BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching. DDECS (2014)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
Automatic complex instruction identification for efficient application mapping onto ASIPs. LASCAS (2014)
Roel Jordans, Lech Józwiak, Henk Corporaal
Instruction-set architecture exploration of VLIW ASIPs using a genetic algorithm. MECO (2014)
Erkan Diken, Roel Jordans, Lech Józwiak, Henk Corporaal
Construction and exploitation of VLIW asips with multiple vector-widths. MECO (2014)
Yahya Jan, Lech Józwiak
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding. Microprocess. Microsystems 38 (2) (2014)
Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths. Microprocess. Microsystems 38 (8) (2014)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
A framework for automatic custom instruction identification on multi-issue ASIPs. INDIN (2014)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak, Henk Corporaal
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. ICA3PP (1) (2013)
Erkan Diken, Rosilde Corvino, Lech Józwiak
Rapid and accurate energy estimation of vector processing in VLIW ASIPs. MECO (2013)
Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
Hardware reuse in modern application-specific processors and accelerators. Microprocess. Microsystems 37 (6-7) (2013)
Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
Exploring processor parallelism: Estimation methods and optimization strategies. DDECS (2013)
Lech Józwiak, Yahya Jan
Hardware Multi-processor Design for Highly-Demanding Applications. ITNG (2013)
Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors. DSD (2013)
Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo, Giuseppe Notarangelo
ASAM: Automatic architecture synthesis and application mapping. Microprocess. Microsystems 37 (8-C) (2013)
Lech Józwiak, Yahya Jan
Design of massively parallel hardware multi-processors for highly-demanding embedded applications. Microprocess. Microsystems 37 (8-D) (2013)
Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal
Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs. MECO (2013)
Lech Józwiak, Jan Madsen
Quality-driven model-based design of multi-processor embedded systems for highlydemanding applications. MECO (2013)
Laura Micconi, Rosilde Corvino, Deepak Gangadharan, Jan Madsen, Paul Pop, Lech Józwiak
Hierarchical DSE for multi-ASIP platforms. MECO (2013)
Nadia Nedjah, Lech Józwiak, Luiza de Macedo Mourelle
Application-specific processors and system-on-chips for embedded and pervasive applications. Microprocess. Microsystems 37 (6-7) (2013)
Francesco Leporati, Lech Józwiak
Preface. Microprocess. Microsystems 37 (8-C) (2013)
Lech Józwiak, Radovan Stojanovic, Budimir Lutovac
Message from the chairs. MECO (2013)
Lech Józwiak
HW/SW architecture co-synthesis of ASIP-based MPSoCs for highly- demanding applications. ISVLSI (2013)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. Microprocess. Microsystems 37 (6-7) (2013)
Lech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo
ASAM: Automatic Architecture Synthesis and Application Mapping. DSD (2012)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. VECPAR (2012)
Rosilde Corvino, Abdoulaye Gamatié, Marc Geilen, Lech Józwiak
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops. ICSAMOS (2012)
Roel Jordans, Rosilde Corvino, Lech Józwiak
Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors. DSD (2012)
Rosilde Corvino, Erkan Diken, Abdoulaye Gamatié, Lech Józwiak
Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study. DSD (2012)
Yahya Jan, Lech Józwiak
Scalable communication architectures for massively parallel hardware multi-processors. J. Parallel Distributed Comput. 72 (11) (2012)
Yahya Jan, Lech Józwiak
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors. VLSI Design 2012 (2012)
Lech Józwiak, Menno Lindwer
Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs. PDP (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak
A parallel architecture for ray-tracing with an embedded intersection algorithm. ISCAS (2011)
Michal Bryk, Lech Józwiak, Wieslaw Kuzmicz
Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits. DSD (2011)
Lech Józwiak
Advanced Architectures for Highly-demanding Embedded and Pervasive Applications. PECCS (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. ICA3PP (2) (2011)
Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD (2011)
Lech Józwiak, Yahya Jan
Quality-driven methodology for demanding accelerator design. ISQED (2010)
Lech Józwiak, Yahya Jan
Architecture Design of Reconfigurable Accelerators for Demanding Applications. ITNG (2010)
Lech Józwiak
Quality-driven SoC architecture synthesis for embedded applications. SoCC (2010)
Lech Józwiak, Nadia Nedjah, Miguel E. Figueroa
Modern development methods and tools for embedded reconfigurable systems: A survey. Integr. 43 (1) (2010)
Yahya Jan, Lech Józwiak
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey. SAMOS (2009)
Lech Józwiak, Nadia Nedjah
Modern Architectures for Embedded Reconfigurable Systems - a Survey. J. Circuits Syst. Comput. 18 (2) (2009)
Yahya Jan, Lech Józwiak
Survey of Advanced CABAC Accelerator Architectures for Future Multimedia. ARC (2009)
Venkatesan Muthukumar, Lech Józwiak
Editorial. J. Syst. Archit. 54 (3-4) (2008)
Lech Józwiak, Alexander Douglas
Hardware Synthesis for Reconfigurable Heterogeneous Pipelined Accelerators. ITNG (2008)
Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
High-Quality Circuit Synthesis for Modern Technologies. ISQED (2008)
Lech Józwiak, Sien-An Ong
Quality-driven model-based architecture synthesis for real-time embedded SoCs. J. Syst. Archit. 54 (3-4) (2008)
Lech Józwiak, Szymon Bieganski
Technology Library Modelling for Information-driven Circuit Synthesis. DSD (2008)
Srikanth Venkataraman, Nagesh Nagapalli, Lech Józwiak
Quality Driven Manufacturing and SOC Designs. ISQED (2007)
Lech Józwiak
Quality-Driven Architecture Synthesis and Power Aware Design of Embedded SoCs. ISQED (2007)
Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems. ICSAMOS (2006)
Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski
Multi-objective Optimal FSM State Assignment. DSD (2006)
Lech Józwiak
Life-Inspired Systems and Their Quality-Driven Design. ARCS (2006)
Lech Józwiak, Sien-An Ong
Quality-Driven Template-Based Architecture Synthesis for Real-time Embedded SoCs. DSD (2006)
Lech Józwiak, Szymon Bieganski, Artur Chojnacki
Information-driven circuit synthesis with the pre-characterized gate libraries. J. Syst. Archit. 51 (6-7) (2005)
Lech Józwiak
Life-Inspired Systems: Assuring Quality in the Era of Complexity, invited. IWSOC (2005)
Henry Selvaraj, Lech Józwiak
Reconfigurable embedded systems: Synthesis, design and application. J. Syst. Archit. 51 (6-7) (2005)
Lech Józwiak, Kaustav Banerjee
Plenary Session 2P. ISQED (2005)
Lech Józwiak, Szymon Bieganski
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates. DSD (2005)
Lech Józwiak
Life-Inspired Systems. DSD (2004)
Lech Józwiak, Szymon Bieganski
Information Trans-Coders in Information-Driven Circuit Synthesis. DSD (2004)
Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods. DSD (2004)
Lech Józwiak, Aleksander Slusarczyk
General decomposition of incompletely specified sequential machines with multi-state behavior realization. J. Syst. Archit. 50 (8) (2004)
Lech Józwiak, Artur Chojnacki
Effective and efficient FPGA synthesis through general functional decomposition. J. Syst. Archit. 49 (4-6) (2003)
Martyn Edwards, Lech Józwiak
Special-issue on reconfigurable systems. J. Syst. Archit. 49 (4-6) (2003)
Lech Józwiak, Aleksander Slusarczyk, Artur Chojnacki
Fast and compact sequential circuits for the FPGA-based reconfigurable systems. J. Syst. Archit. 49 (4-6) (2003)
Lech Józwiak, Szymon Bieganski, Artur Chojnacki
Information-driven Library-based Circuit Synthesis. DSD (2003)
Lech Józwiak
Advanced AI Search Techniques in Modern Digital Circuit Synthesis. Artif. Intell. Rev. 20 (3-4) (2003)
Martyn Edwards, Lech Józwiak
Preface. J. Syst. Archit. 49 (12-15) (2003)
Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture. IEEE Micro 22 (3) (2002)
Lech Józwiak, Aleksander Slusarczyk, Marek A. Perkowski
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits. VLSI Design 2002 (1) (2002)
Marek A. Perkowski, David Foote, Qihong Chen, Anas Al-Rabadi, Lech Józwiak
Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach. IEEE Micro 22 (3) (2002)
Lech Józwiak, Adam Postula
Genetic engineering versus natural evolution: Genetic algorithms with deterministic operators. J. Syst. Archit. 48 (1-3) (2002)
Aleksander Slusarczyk, Lech Józwiak
Interoperability and Quality of New EDA Tools for Sequential Logic Synthesis. ISQED (2002)
Marek A. Perkowski, Lech Józwiak, William Zhao
Symbolic two-dimensional minimization of strongly unspecified finite state machines. J. Syst. Archit. 47 (1) (2001)
Lech Józwiak, Artur Chojnacki
High-quality sub-function construction in functional decomposition based on information relationship measures. DATE (2001)
Artur Chojnacki, Lech Józwiak
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. ISQED (2001)
Lech Józwiak
Quality-driven design in the system-on-a-chip era: Why and how? J. Syst. Archit. 47 (3-4) (2001)
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
Regular Realization of Symmetric Functions Using Reversible Logic. DSD (2001)
Mariusz Rawski, Lech Józwiak, Tadeusz Luba
Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. J. Syst. Archit. 47 (2) (2001)
Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk
Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis. DSD (2001)
Lech Józwiak
Modern methods and tools in digital system design. J. Syst. Archit. 47 (3-4) (2001)
Lech Józwiak, Artur Chojnacki
Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures. DSD (2001)
Lech Józwiak
Quality-Driven System-on-a-Chip Design. ISQED (2000)
Lech Józwiak, Aleksander Slusarczyk
A New State Assignment Method Targeting FPGA Implementations. EUROMICRO (2000)

Lech Józwiak.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Lech Józwiak