Henry Selvaraj

Publication Activity (10 Years)

Years Active: 1995-2022
Publications (10 Years): 6

Top Topics

Matrix Multiplication

Energy Consumption

Fpga Implementation

Distributed Computing

Top Venues

Publications

Ranju Mandal, Brijesh K. Verma, Basim Azam, Henry Selvaraj
A Novel Optimized Context-Based Deep Architecture for Scene Parsing. ICONIP (6) (2022)
Henry Selvaraj, Nikita Ramesh Wanjale
Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models. ICSEng (2017)
Grzegorz Chmaj, Henry Selvaraj
Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated Mesh and Fat Tree. ICSEng (2017)
Ahmed Khamis, Dawid Zydek, Henry Selvaraj
Improved Genetic Algorithm for Finite-Horizon Optimal Control of Nonlinear Systems. ICSEng (2017)
D. Selvathi, Henry Selvaraj
FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals. ICSEng (2017)
Grzegorz Chmaj, Henry Selvaraj
Energy-Efficient Computing Solutions for Internet of Things with ZigBee Reconfigurable Devices. Int. J. Softw. Innov. 4 (1) (2016)
Grzegorz Chmaj, Henry Selvaraj
Concentrated mesh and fat tree usage efficiency in System-on-Chip based multiprocessor distributed processing architectures. MECO (2015)
Grzegorz Chmaj, Henry Selvaraj
Energy-efficient distributed computing solutions for Internet of Things with ZigBee devices. ICIS (2015)
D. Selvathi, Henry Selvaraj, J. Dharani
FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm. Int. J. Comput. Intell. Appl. 14 (2) (2015)
Luka Daoud, Dawid Zydek, Henry Selvaraj
A Survey on Design and Implementation of Floating Point Adder in FPGA. ICSEng (2014)
Grzegorz Chmaj, Henry Selvaraj
UAV Cooperative Data Processing Using Distributed Computing Platform. ICSEng (2014)
Grzegorz Chmaj, Henry Selvaraj
Distributed Processing Applications for UAV/drones: A Survey. ICSEng (2014)
Dawid Krol, Dawid Zydek, Henry Selvaraj
Matrix Multiplication in Multiphysics Systems Using CUDA. ICSS (2013)
Luka Daoud, Dawid Zydek, Henry Selvaraj
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. ICSS (2013)
Mohammad Shokrolah Shirazi, Brendan Morris, Henry Selvaraj
Fast FPGA-based fault injection tool for embedded processors. ISQED (2013)
Grzegorz Chmaj, Henry Selvaraj, Laxmi P. Gewali
Tracker-Node Model for Energy Consumption in Reconfigurable Processing Systems. ICSS (2013)
Bin Liu, Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali
Accelerating High Performance Computing Applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs. PDCAT (2012)
Grzegorz Chmaj, Dawid Zydek, Yehia Zakarya Elhalwagy, Henry Selvaraj
Overlay-NoC and H-Phy based computing using modern Chip Multiprocessors. EIT (2012)
Dawid Zydek, Grzegorz Chmaj, Henry Selvaraj
Extended Analysis of Resource Assignment in Modern Chip Multiprocessors. ICSEng (2011)
Bartosz Kajak, Laxmi P. Gewali, Henry Selvaraj
Ear-Slicing and Quality Triangulation. ICSEng (2011)
G. Wiselin Jiji, Henry Selvaraj, G. Evelin Suji
Supervised Classification of White Blood Cells by Fusion of Color Texture Features and Neural Network. Int. J. Comput. Intell. Appl. 10 (4) (2011)
Dawid Zydek, Henry Selvaraj
Fast and efficient processor allocation algorithm for torus-based chip multiprocessors. Comput. Electr. Eng. 37 (1) (2011)
Dawid Zydek, Henry Selvaraj, Grzegorz Borowik, Tadeusz Luba
Energy characteristic of a processor allocator and a network-on-chip. Int. J. Appl. Math. Comput. Sci. 21 (2) (2011)
D. Selvathi, Henry Selvaraj, S. Thamarai Selvi
Hybrid Approach for Brain Tumor Segmentation in Magnetic Resonance Images Using Cellular Neural Networks and Optimization Techniques. Int. J. Comput. Intell. Appl. 9 (1) (2010)
Dawid Zydek, Henry Selvaraj, Laxmi P. Gewali
Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors. ITNG (2010)
Dawid Zydek, Henry Selvaraj
Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors. Microprocess. Microsystems 34 (1) (2010)
Laxmi P. Gewali, Dan Mazzella, Henry Selvaraj
Constrained Disjoint Paths in Geometric Networks. Int. J. Comput. Intell. Appl. 8 (2) (2009)
Henry Selvaraj, S. Arivazhagan
Editorial: Applications of Computational Intelligence. Int. J. Comput. Intell. Appl. 8 (2) (2009)
Dawid Zydek, Henry Selvaraj
Processor Allocation Problem for NoC-Based Chip Multiprocessors. ITNG (2009)
A. R. Nadira Banu Kamal, S. Thamarai Selvi, Henry Selvaraj
Iteration-Free Fractal Coding for Image Compression Using Genetic Algorithm. Int. J. Comput. Intell. Appl. 7 (4) (2008)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints. Integr. 40 (2) (2007)
Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj
An efficient variable partitioning approach for functional decomposition of circuits. J. Syst. Archit. 53 (1) (2007)
Min Tun, Laxmi P. Gewali, Henry Selvaraj
Interference Aware Routing in Sensor Network. ITNG (2007)
Dongxin Wen, Ling Wang, Yingtao Jiang, Henry Selvaraj, Xiao-Zong Yang
Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages. Int. J. Comput. Their Appl. 14 (2) (2007)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages. J. Supercomput. 35 (1) (2006)
D. Selvathi, S. Thamarai Selvi, Henry Selvaraj
Abnormality Detection in Brain MR Images Using Minimum Error Thresholding Method. Int. J. Comput. Intell. Appl. 6 (2) (2006)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba, Piotr Szotkowski
Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition. Int. J. Comput. Intell. Appl. 6 (2) (2006)
Henry Selvaraj, S. Thamarai Selvi, D. Selvathi, R. Ramkumar
Support Vector Machine Based Automatic Classification of Human Brain Using MR Image Features. Int. J. Comput. Intell. Appl. 6 (3) (2006)
Henry Selvaraj, Piotr Sapiecha, Mariusz Rawski, Tadeusz Luba
Functional Decomposition - the Value and Implication for Both Neural Networks and Digital Designing. Int. J. Comput. Intell. Appl. 6 (1) (2006)
Henry Selvaraj, Pawel Tomaszewicz, Mariusz Rawski, Tadeusz Luba
Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. ITCC (2) (2005)
Henry Selvaraj, Lech Józwiak
Reconfigurable embedded systems: Synthesis, design and application. J. Syst. Archit. 51 (6-7) (2005)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Multiple voltage synthesis scheme for low power design under timing and resource constraints. Integr. Comput. Aided Eng. 12 (4) (2005)
Venkatesan Muthukumar, Bharath Radhakrishnan, Henry Selvaraj
Multiple voltage and frequency scheduling for power minimization. J. Syst. Archit. 51 (6-7) (2005)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
An application of functional decomposition in ROM-based FSM implementation in FPGA devices. J. Syst. Archit. 51 (6-7) (2005)
Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. DSD (2005)
Piotr Sapiecha, Henry Selvaraj, Jaroslaw Stanczak, Krzysztof Sep, Tadeusz Luba
A Hybrid Approach to a Classification Problem. Intelligent Information Systems (2004)
Jianhong Li, Laxmi P. Gewali, Henry Selvaraj, Muthukumar Venkatesan
Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. DSD (2004)
Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki
Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. DSD (2004)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms. ITCC (2) (2004)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Synthesis scheme for low power designs with multiple supply voltages by tabu search. ISCAS (5) (2004)
Ling Wang, Henry Selvaraj
A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. DSD (2003)
Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. DSD (2003)
Ling Wang, Yingtao Jiang, Henry Selvaraj
Scheduling and Optimal Voltage Selection with Multiple Supply Voltages under Resource Constraints. VLSI (2003)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. DSD (2003)
Muthukumar Venkatesan, Henry Selvaraj
Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. VLSI Design (2003)
Ling Wang, Henry Selvaraj
Performance Driven Circuit Clustering and Partitioning. ITCC (2002)
Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. ITCC (2002)
Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
A variable partition approach for disjoint decomposition. ISCAS (5) (2001)
Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
Functional Decomposition and Its Applications in Machine Learning and Neural Networks. Int. J. Comput. Intell. Appl. 1 (3) (2001)
Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj
An Input-Output Encoding Approach for Serial Decomposition. SBCCI (2000)
Piotr Sapiecha, Henry Selvaraj, Michal Pleban
Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis. Rough Sets and Current Trends in Computing (2000)
Henry Selvaraj, B. Li
A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools. EUROMICRO (2000)
Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
An Improved Column Compatibility Approach for Partition Based Functional Decomposition. EUROMICRO (2000)
Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba
Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. VLSI Design (1998)
Henry Selvaraj, Muthukumar Venkatesan
A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool. EUROMICRO (1998)
Henry Selvaraj, Tadeusz Luba
A balanced multilevel decomposition method. ED&TC (1995)
Tadeusz Luba, Henry Selvaraj
A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis. VLSI Design 3 (3-4) (1995)