A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages.

Ling Wang Henry Selvaraj

Published in: DSD (2003)

Keyphrases

low power
high speed
power consumption
logic circuits
low cost
cmos technology
power reduction
delay insensitive
vlsi circuits
power dissipation
gate array
mixed signal
single chip
vlsi architecture
high power
scheduling algorithm
image sensor
nm technology