Luka Daoud

Publication Activity (10 Years)

Years Active: 2013-2022
Publications (10 Years): 17

Top Topics

High Level Synthesis

Top Venues

Microprocess. Microsystems

Publications

Luka Daoud, Nader Rafla
Energy-Efficient Black Hole Router Detection in Network-on-Chip. SOCC (2022)
Luka Daoud, Nader Rafla
Efficient mitigation technique for Black Hole router attack in Network-on-Chip. Microprocess. Microsystems 94 (2022)
Fady Hussein, Luka Daoud, Nader Rafla
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA. Microprocess. Microsystems 74 (2020)
Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching, . CoRR (2020)
Luka Daoud, Muhammad Kamran Latif, H. S. Jacinto, Nader Rafla
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching. Microprocess. Microsystems 72 (2020)
Luka Daoud, Nader Rafla
Analysis of Black Hole Router Attack in Network-on-Chip. MWSCAS (2019)
Luka Daoud, Nader Rafla
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip. SoCC (2019)
Luka Daoud, Fady Hussein, Nader Rafla
Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS). CATA (2019)
Luka Daoud, Nader Rafla
Detection and prevention protocol for black hole attack in network-on-chip. NOCS (2019)
Luka Daoud, Muhammad Kamran Latif, Nader Rafla
SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only). FPGA (2018)
Luka Daoud
Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges. MWSCAS (2018)
Luka Daoud, Nader Rafla
Routing Aware and Runtime Detection for Infected Network-on-Chip Routers. MWSCAS (2018)
Luka Daoud, Fady Hussein, Nader Rafla
Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration. MWSCAS (2018)
Muhammad Kamran Latif, H. S. Jacinto, Luka Daoud, Nader Rafla
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol. MWSCAS (2018)
Fady Hussein, Luka Daoud, Nader Rafla
HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only). FPGA (2018)
H. S. Jacinto, Luka Daoud, Nader Rafla
High level synthesis using vivado HLS for optimizations of SHA-3. MWSCAS (2017)
Danyal Mohammadi, Luka Daoud, Nader Rafla, Said Ahmed-Zaid
Zynq-based SoC implementation of an induction machine control algorithm. MWSCAS (2016)
Luka Daoud, Dawid Zydek, Henry Selvaraj
A Survey on Design and Implementation of Floating Point Adder in FPGA. ICSEng (2014)
Luka Daoud, Dawid Zydek, Henry Selvaraj
A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. ICSS (2013)