A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA.
Fady HusseinLuka DaoudNader RaflaPublished in: Microprocess. Microsystems (2020)
Keyphrases
- systolic array
- evolvable hardware
- reconfigurable architecture
- parallel architecture
- data flow
- digital circuits
- parallel processing
- evolutionary algorithm
- reconfigurable hardware
- hardware implementation
- evolutionary computation
- bio inspired
- low cost
- shared memory
- distributed memory
- object oriented
- genetic programming
- particle swarm optimization
- load balancing
- databases
- multi objective
- relational databases
- data mining