Tadeusz Luba

Publication Activity (10 Years)

Years Active: 1991-2022
Publications (10 Years): 4

Top Topics

Wave Propagation

Top Venues

Comput. Aided Civ. Infrastructure Eng.

Publications

Dariusz Wasicki, Tadeusz Luba
Data Analysis and Mining Using Logical Synthesis Methods. MIXDES (2022)
Grzegorz Borowik, Tadeusz Luba, Ryszard Klempous
Comparison of algorithms for dimensionality reduction and their application to index generation functions. SoSE (2020)
Tomasz Mazurkiewicz, Tadeusz Luba
Non-disjoint Decomposition Using r-admissibility and Graph Coloring and Its Application in Index Generation Functions Minimization. MIXDES (2019)
Tomasz Mazurkiewicz, Tadeusz Luba
Linear and Non-linear Decomposition of Index Generation Functions. MIXDES (2019)
Tomasz Wandowski, Pawel Malinowski, Wieslaw Ostachowicz, Mariusz Rawski, Pawel Tomaszewicz, Tadeusz Luba, Grzegorz Borowik
Embedded Damage Localization Subsystem Based on Elastic Wave Propagation. Comput. Aided Civ. Infrastructure Eng. 30 (8) (2015)
Michal Mankowski, Tadeusz Luba, Cezary Jankowski
Evaluation of Decision Table Decomposition Using Dynamic Programming Classifiers. CS&P (2015)
Grzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba
Rule Induction Based on Logic Synthesis Methods. ICSEng (2014)
Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba
Fixed Polarity Linearly Independent Expansions for the Representation of Quaternary Functions. J. Multiple Valued Log. Soft Comput. 19 (4) (2012)
Grzegorz Borowik, Tadeusz Luba, Dawid Zydek
Reduction of Knowledge Representation Using Logic Minimization Techniques. ICSEng (2011)
Dawid Zydek, Henry Selvaraj, Grzegorz Borowik, Tadeusz Luba
Energy characteristic of a processor allocator and a network-on-chip. Int. J. Appl. Math. Comput. Sci. 21 (2) (2011)
Grzegorz Borowik, Tadeusz Luba, Pawel Tomaszewicz
On Memory Capacity to Implement Logic Functions. EUROCAST (2) (2011)
Grzegorz Borowik, Tadeusz Luba
Decomposing Pattern Matching Circuit. EUROCAST (2009)
Grzegorz Borowik, Tadeusz Luba, Bogdan J. Falkowski
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. DDECS (2009)
Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba
Decision diagram based computation of linearly independent ternary arithmetic transform spectra. EUSIPCO (2009)
Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba
Two classes of fixed polarity linearly independent arithmetic transforms for quaternary functions. EUSIPCO (2009)
Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba
Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure. ISMVL (2009)
Mariusz Rawski, Tadeusz Luba, Bogdan J. Falkowski
Logic synthesis method for FPGAs with embedded memory blocks. ISCAS (2008)
Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba
Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms. ISMVL (2008)
Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba
Family of Fastest Linearly Independent Transforms over GF(3): Generation, Relations, and Hardware Implementation. J. Multiple Valued Log. Soft Comput. 13 (4-6) (2007)
Grzegorz Borowik, Bogdan J. Falkowski, Tadeusz Luba
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGAs. DDECS (2007)
Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba
Properties and relations of new fastest linearly independent arithmetic transforms for ternary functions. EUSIPCO (2007)
Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba
New Fastest Linearly Independent Transforms over GF(3). ISMVL (2007)
Bogdan J. Falkowski, Cicilia C. Lozano, Tadeusz Luba
Efficient Algorithm for Calculation of Quaternardy Fixed Polarity Arithmetic Expansions. ISMVL (2007)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba, Piotr Szotkowski
Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition. Int. J. Comput. Intell. Appl. 6 (2) (2006)
Henry Selvaraj, Piotr Sapiecha, Mariusz Rawski, Tadeusz Luba
Functional Decomposition - the Value and Implication for Both Neural Networks and Digital Designing. Int. J. Comput. Intell. Appl. 6 (1) (2006)
Henry Selvaraj, Pawel Tomaszewicz, Mariusz Rawski, Tadeusz Luba
Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. ITCC (2) (2005)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
An application of functional decomposition in ROM-based FSM implementation in FPGA devices. J. Syst. Archit. 51 (6-7) (2005)
Mariusz Rawski, Pawel Tomaszewicz, Henry Selvaraj, Tadeusz Luba
Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. DSD (2005)
Piotr Sapiecha, Henry Selvaraj, Jaroslaw Stanczak, Krzysztof Sep, Tadeusz Luba
A Hybrid Approach to a Classification Problem. Intelligent Information Systems (2004)
Janusz A. Brzozowski, Tadeusz Luba
Decomposition of Boolean Functions Specified by Cubes. J. Multiple Valued Log. Soft Comput. 9 (4) (2003)
Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. DSD (2003)
Mariusz Rawski, Henry Selvaraj, Tadeusz Luba
An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices. DSD (2003)
Henry Selvaraj, Mariusz Rawski, Tadeusz Luba
FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. ITCC (2002)
Mariusz Rawski, Lech Józwiak, Tadeusz Luba
Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures. J. Syst. Archit. 47 (2) (2001)
Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba
Functional Decomposition and Its Applications in Machine Learning and Neural Networks. Int. J. Comput. Intell. Appl. 1 (3) (2001)
Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, Vlad P. Shmerko, Joanna Kolodziejczyk
Application of Design Style in Evolutionary Multi-Level Networks Synthesis. EUROMICRO (2000)
Tadeusz Luba, Claudio Moraga, Svetlana N. Yanushkevich, M. Opoka, Vlad P. Shmerko
Evolutionary Multi-Level Network Synthesis in Given Design Style. ISMVL (2000)
Rafal Rzechowski, Tadeusz Luba, Lech Józwiak
Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. EUROMICRO (1999)
Mariusz Rawski, Lech Józwiak, Tadeusz Luba
The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. EUROMICRO (1999)
Mariusz Rawski, Lech Józwiak, Tadeusz Luba
Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. EUROMICRO (1999)
Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba
Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. VLSI Design (1998)
Mariusz Rawski, Tadeusz Luba, Lech Józwiak, Artur Chojnacki
Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measure. EUROMICRO (1998)
Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
Decomposition of Multiple-Valued Relations . ISMVL (1997)
Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL (1997)
Henry Selvaraj, Tadeusz Luba
A balanced multilevel decomposition method. ED&TC (1995)
Tadeusz Luba
Decomposition of Multiple-Valued Functions. ISMVL (1995)
Tadeusz Luba, Henry Selvaraj
A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis. VLSI Design 3 (3-4) (1995)
Tadeusz Luba
Multi-level logic synthesis based on decomposition. Microprocess. Microsystems 18 (8) (1994)
Tadeusz Luba, Robert Lasocki, Janusz Rybnik
An Implementation of Decomposition Algorithm and its Application in Information System Analysis and Logic Synthesis. RSKD (1993)
Tadeusz Luba, K. Górski, Leszek B. Wronski
ROM-based finite state machines with PLA address modifiers. EURO-DAC (1992)
Tadeusz Luba, Jerzy Kalinowski, Krzysztof Jasinski
PLATO: a CAD tool for logic synthesis based on decomposition. EURO-DAC (1991)