Alexandre Solon Nery

Publication Activity (10 Years)

Years Active: 2009-2021
Publications (10 Years): 16

Top Topics

Stream Processing

Computationally Intensive

Top Venues

Concurr. Comput. Pract. Exp.

IPDPS Workshops

Int. J. Grid Util. Comput.

Publications

Carlos Antônio Campos Jorge, Alexandre Solon Nery, Alba C. M. A. Melo, Alfredo Goldman
A CPU-FPGA heterogeneous approach for biological sequence comparison using high-level synthesis. Concurr. Comput. Pract. Exp. 33 (4) (2021)
Brunno F. Goldstein, Victor da Cruz Ferreira, Sudarshan Srinivasan, Dipankar Das, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França
A Lightweight Error-Resiliency Mechanism for Deep Neural Networks. ISQED (2021)
Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu
Preventing DNN Model IP Theft via Hardware Obfuscation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (2) (2021)
Adrianno Sampaio, Alexandre da Costa Sena, Alexandre Solon Nery
Enabling heterogeneous ray-tracing acceleration in edge/cloud architectures. Concurr. Comput. Pract. Exp. 33 (11) (2021)
Brunno F. Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago de Araújo, Victor da Cruz Ferreira, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França
Reliability Evaluation of Compressed Deep Learning Models. LASCAS (2020)
Leandro Santiago de Araújo, Victor da Cruz Ferreira, Brunno Figueiroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu, Felipe Maia Galvão França
Hardware-Accelerated Similarity Search with Multi-Index Hashing. DASC/PiCom/DataCom/CyberSciTech (2019)
Alexandre Solon Nery, Alexandre da Costa Sena, Leandro S. Guedes
An efficient pathfinding system in FPGA for edge/fog computing. Int. J. Grid Util. Comput. 10 (3) (2019)
Victor da Cruz Ferreira, Alexandre Solon Nery, Leandro A. J. Marzulo, Leandro Santiago, Diego Fonseca Pereira de Souza, Brunno F. Goldstein, Felipe M. G. França, Vladimir Castro Alves
A Feasible FPGA Weightless Neural Accelerator. ISCAS (2019)
Adrianno Sampaio, Alexandre da Costa Sena, Alexandre Solon Nery
A Re-Configurable Ray-Triangle Vector Accelerator for Emerging Fog Architectures. IPDPS Workshops (2019)
Leandro Rouberte, Alexandre da Costa Sena, Alexandre Solon Nery, Leandro A. J. Marzulo, Tiago A. O. Alves, Felipe M. G. França
DF-DTM: Dynamic Task Memoization and reuse in dataflow. Concurr. Comput. Pract. Exp. 31 (18) (2019)
Leandro A. J. Marzulo, Alexandre da Costa Sena, Alexandre Solon Nery, Cristiana Bentes, Igor Machado Coelho, Maria Clicia Stelling de Castro, Saulo T. Oliveira, Tiago A. O. Alves, Felipe M. G. França
DTM@GPU: Characterizing and evaluating trace redundancy in GPU. Concurr. Comput. Pract. Exp. 31 (18) (2019)
Marcos Paulo Rocha, Felipe M. G. França, Alexandre Solon Nery, Leandro S. Guedes
An optimised dataflow engine for GPGPU stream processing. Int. J. Grid Util. Comput. 10 (3) (2019)
Alexandre Solon Nery, Alexandre da Costa Sena
Efficient A* Co-processor for Reconfigurable Gaming Devices. SBGames (2018)
Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe Maia Galvão França
A Smart Disk for In-Situ Face Recognition. IPDPS Workshops (2018)
Alexandre Solon Nery, Alexandre da Costa Sena, Leandro S. Guedes
Efficient Pathfinding Co-Processors for FPGAs. SBAC-PAD (Workshops) (2017)
Marcos Paulo Rocha, Felipe M. G. França, Alexandre Solon Nery, Leandro S. Guedes
Dataflow Programming for Stream Processing. SBAC-PAD (Workshops) (2017)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
Automatic complex instruction identification for efficient application mapping onto ASIPs. LASCAS (2014)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak, Henk Corporaal
A framework for automatic custom instruction identification on multi-issue ASIPs. INDIN (2014)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak, Henk Corporaal
A Reconfigurable Ray-Tracing Multi-Processor SoC with Hardware Replication-Aware Instruction Set Extension. ICA3PP (1) (2013)
Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
Hardware reuse in modern application-specific processors and accelerators. Microprocess. Microsystems 37 (6-7) (2013)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França
Efficient hardware implementation of Ray Tracing based on an embedded software for intersection computation. J. Syst. Archit. 59 (3) (2013)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Parallel processing of intersections for ray-tracing in application-specific processors and GPGPUs. Microprocess. Microsystems 37 (6-7) (2013)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Interactive Volume Rendering Based on Ray-Casting for Multi-core Architectures. VECPAR (2012)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França, Lech Józwiak
A parallel architecture for ray-tracing with an embedded intersection algorithm. ISCAS (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations. DSD (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França, Lech Józwiak
Massively Parallel Identification of Intersection Points for GPGPU Ray Tracing. ICA3PP (2) (2011)
Alexandre Solon Nery, Lech Józwiak, Menno Lindwer, Mauro Cocco, Nadia Nedjah, Felipe M. G. França
Hardware Reuse in Modern Application-Specific Processors and Accelerators. DSD (2011)
Alexandre Solon Nery, Nadia Nedjah, Felipe Maia Galvão França
GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. DSD (2009)
Alexandre Solon Nery, Nadia Nedjah, Felipe M. G. França
A massively parallel hardware architecture for ray-tracing. Int. J. High Perform. Syst. Archit. 2 (1) (2009)