Edith Beigné

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 50

Top Venues

ISSCC

IEEE J. Solid State Circuits

PATMOS

NEWCAS

Publications

Tony F. Wu, Huichu Liu, Huseyin Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné
11.2 A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint. ISSCC (2024)
Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. IEEE Micro 44 (2) (2024)
Karl Kaiser, Dinesh Patil, Edith Beigné
A prototype 5nm custom sensor SoC for Augmented Reality/Virtual Reality targeting Smartglasses with embedded computer vision, audio, security and ML. VLSI Technology and Circuits (2023)
Matheus Trevisan Moreira, William Koven, Tony F. Wu, H. Ekin Sumbul, Edith Beigné
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ASYNC (2023)
Lita Yang, Robert M. Radway, Yu-Hsin Chen, Tony F. Wu, Huichu Liu, Elnaz Ansari, Vikas Chandra, Subhasish Mitra, Edith Beigné
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications. IEEE Micro 42 (6) (2022)
Daniel H. Morris, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. VLSI Technology and Circuits (2022)
H. Ekin Sumbul, Tony F. Wu, Yuecheng Li, Syed Shakib Sarwar, William Koven, Eli Murphy-Trotzky, Xingxing Cai, Elnaz Ansari, Daniel H. Morris, Huichu Liu, Doyun Kim, Edith Beigné
System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars. CICC (2022)
Linyan Mei, Huichu Liu, Tony F. Wu, H. Ekin Sumbul, Marian Verhelst, Edith Beigné
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE (2022)
Tony F. Wu, Doyun Kim, Daniel H. Morris, Edith Beigné
Evaluation of Low-Voltage SRAM for Error-Resilient Augmented Reality Applications. SiPS (2021)
Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
Spiking Neural Networks Hardware Implementations and Challenges: a Survey. CoRR (2020)
Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits (2020)
Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, H.-P. Charles
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. VLSI-SoC (2019)
Sung-Gun Cho, Edith Beigné, Zhengya Zhang
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC (2019)
Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. IEEE J. Solid State Circuits 54 (4) (2019)
Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné
Spiking Neural Networks Hardware Implementations and Challenges: A Survey. ACM J. Emerg. Technol. Comput. Syst. 15 (2) (2019)
Tony F. Wu, Binh Q. Le, Robert Radway, Andrew Bartolo, William Hwang, Seungbin Jeong, Haitong Li, Pulkit Tandon, Elisa Vianello, Pascal Vivet, Etienne Nowak, Mary Wootters, H.-S. Philip Wong, Mohamed M. Sabry Aly, Edith Beigné, Subhasish Mitra
A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques. ISSCC (2019)
Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS (2019)
Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects. 3DIC (2019)
Daniele Jahier Pagliari, Yves Durand, David Coriat, Edith Beigné, Enrico Macii, Massimo Poncino
Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Anthony Quelen, Gaël Pillonnet, Philippe Flatresse, Edith Beigné
automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. ISSCC (2018)
Pascal Vivet, Sébastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. ICECS (2018)
Edith Beigné
FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience. ESSCIRC (2018)
Edith Beigné
FDSOI circuit design for high energy efficiency: Wide operating range and ULP applications - a 7-year experience. ESSDERC (2018)
Dusan M. Stipanovic, Boris Murmann, Matteo Causo, Aleksandra Lekic, Vicenç Rúbies Royo, Claire J. Tomlin, Edith Beigné, Sébastien Thuries, Mykhailo Zarudniev, Suzanne Lesecq
Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model. ISCAS (2018)
Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. NANOARCH (2018)
Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. VLSI Circuits (2018)
Youngmin Shin, Phillip J. Restle, Edith Beigné
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. ISSCC (2018)
Mickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné
Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. ICECS (2018)
Imed Jani, Didier Lattard, Pascal Vivet, Lucile Arnaud, Edith Beigné
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects. ETS (2018)
Dennis Sylvester, Koji Hirairi, Edith Beigné
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. ISSCC (2018)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37 (5) (2017)
Yasuhisa Shimazaki, John Maneatis, Edith Beigné
Session 8 overview: Digital PLLs and security circuits. ISSCC (2017)
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Imed Jani, Didier Lattard, Pascal Vivet, Edith Beigné
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC. NEWCAS (2017)
Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS (2017)
Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits 52 (1) (2017)
Kathy Wilcox, Youngmin Shin, Edith Beigné
Session 26 overview: Processor-power management and clocking. ISSCC (2017)
Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Melanie Brocard, David Turgis, Edith Beigné
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Daniele Jahier Pagliari, Yves Durand, David Coriat, Anca Molnos, Edith Beigné, Enrico Macii, Massimo Poncino
A methodology for the design of dynamic accuracy operators by runtime back bias. DATE (2017)
Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. 13 (3) (2017)
Thomas Mesquida, Alexandre Valentian, David Bol, Edith Beigné
Architecture exploration of a fixed point computation unit using precise timing spiking neurons. PATMOS (2017)
Laurent Alacoque, Sébastien Martin, Wilfried Rabaud, Edith Beigné, Antoine Dupret, Bertrand Dupont
A 128x128, 34μm pitch, 8.9mW, 190mK NETD, TECless Uncooled IR bolometer image sensor with column-wise processing. IMSE (2017)
Atsuki Inoue, Dennis Sylvester, Edith Beigné
Session 20 overview: Digital voltage regulators and low-power techniques. ISSCC (2017)
Pierre-Emmanuel Gaillardon, Romain Magni, Luca Gaetano Amarù, Mehdi Hasan, Ross Walker, Berardi Sensale Rodriguez, Jean-Frédéric Christmann, Edith Beigné
Three-Independent-Gate Transistors: Opportunities in digital, analog and RF applications. LATS (2016)
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. ICICDT (2016)
Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC (2016)
Edith Beigné, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51 (1) (2016)
Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips (2016)
Mauricio Altieri, Suzanne Lesecq, Edith Beigné, Olivier Héron, Diego Puschini
Tracking BTI and HCI effects at circuit-level in adaptive systems. NEWCAS (2016)
Pierre-Emmanuel Gaillardon, Edith Beigné, Suzanne Lesecq, Giovanni De Micheli
A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems. ACM J. Emerg. Technol. Comput. Syst. 12 (2) (2015)
Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS (2015)
Eldar Zianbetov, Edith Beigné, Gregory di Pendina
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology. ASYNC (2015)
Jeremy Lopes, Gregory di Pendina, Eldar Zianbetov, Edith Beigné, Lionel Torres
Radiative Effects on MRAM-Based Non-Volatile Elementary Structures. ISVLSI (2015)
Emilie Garat, David Coriat, Edith Beigné, Leandro Stefanazzi
Unified Power Format (UPF) methodology in a vendor independent flow. PATMOS (2015)
Soundous Chairat, Edith Beigné, Marc Belleville
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS (2015)
Edith Beigné, Jean-Frédéric Christmann, Alexandre Valentian, Olivier Billoint, Esteve Amat, Dominique Morche
UTBB FDSOI technology flexibility for ultra low power internet-of-things applications. ESSDERC (2015)
Mauricio Altieri, Suzanne Lesecq, Diego Puschini, Olivier Héron, Edith Beigné, Jorge Rodas
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor. PATMOS (2015)
Florent Berthier, Edith Beigné, Pascal Vivet, Olivier Sentieys
Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller. NEWCAS (2015)
Edith Beigné, Jean-Frédéric Christmann, Eldar Zianbetov, Gregory di Pendina
Ultra-low power volatile and non-volatile asynchronous circuits using back-biasing. ECCTD (2015)
Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50 (1) (2015)
Lionel Vincent, Edith Beigné, Suzanne Lesecq, Julien Mottin, David Coriat, Philippe Maurine
Dynamic Variability Monitoring Using Statistical Tests for Energy Efficient Adaptive Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran
H.264/AVC hardware encoders and low-power features. APCCAS (2014)
Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC (2014)
Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran
FIFO-level-based power management and its application to an H.264 encoder. IECON (2014)
Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres
Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC (2014)
Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits 49 (7) (2014)
Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid, Bertrand Pelloux-Prayer, Anuj Grover, Sylvain Clerc, Philippe Roche, Julien Le Coz, Sylvain Engels, Robin Wilson
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE (2013)
Jérémie Hamon, Edith Beigné
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology. ASYNC (2013)
Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE (2013)
Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Pascal Benoit, Lionel Torres
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. PATMOS (2013)
Sylvain Durand, Suzanne Lesecq, Edith Beigné, Diego Puschini
Event-based DVFS control in GALS-ANoC MPSoCs. ACC (2013)
Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné
Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. VLSI-SoC (2013)
Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC (2013)
Lionel Vincent, Suzanne Lesecq, Philippe Maurine, Edith Beigné
Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov tests. CCA (2012)
Smriti Joshi, Anne Lombardot, Philippe Flatresse, Carmelo D'Agostino, Andre Juge, Edith Beigné, Stéphane Girard
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. J. Low Power Electron. 8 (1) (2012)
Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Jérôme Willemin, Christian Piguet
Energy harvesting and power management for autonomous sensor nodes. DAC (2012)
Lionel Vincent, Philippe Maurine, Suzanne Lesecq, Edith Beigné
Embedding statistical tests for on-chip dynamic voltage and temperature monitoring. DAC (2012)
Yvain Thonnart, Edith Beigné, Pascal Vivet
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ASYNC (2012)
Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Christian Piguet
Event-driven asynchronous voltage monitoring in energy harvesting platforms. NEWCAS (2012)
Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems. IEEE Des. Test Comput. 28 (5) (2011)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42 (5) (2011)
Sylvain Durand, Suzanne Lesecq, Edith Beigné, Christian Fabre, Lionel Vincent, Diego Puschini
Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints. FMCO (2011)
Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. 7 (3) (2011)
Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling. J. Low Power Electron. 7 (2) (2011)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6 (1) (2010)
Pascal Vivet, Edith Beigné, Hugo Lebreton, Nacer-Eddine Zergainoh
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS. PATMOS (2010)
Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Nicolas Leblond, Pascal Vivet, G. Waltisperger, Jérôme Willemin
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems. ASYNC (2010)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS (2009)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS (2009)
Yvain Thonnart, Edith Beigné, Pascal Vivet
Design and Implementation of a GALS Adapter for ANoC Based Architectures. ASYNC (2009)
Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
Power Reduction of Asynchronous Logic Circuits Using Activity Detection. IEEE Trans. Very Large Scale Integr. Syst. 17 (7) (2009)
Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits 44 (4) (2009)
Edith Beigné, Fabien Clermidy, Sylvain Miermont, Pascal Vivet
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC. NOCS (2008)
Edith Beigné, Fabien Clermidy, Sylvain Miermont, Alexandre Valentian, Pascal Vivet, S. Barasinski, F. Blisson, N. Kohli, S. Kumar
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. ESSCIRC (2008)
Alexandre Valentian, Edith Beigné
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability. IEEE J. Solid State Circuits 43 (7) (2008)
Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction. ASYNC (2008)
Didier Lattard, Edith Beigné, Fabien Clermidy, Yves Durand, Romain Lemaire, Pascal Vivet, Friedbert Berens
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip. IEEE J. Solid State Circuits 43 (1) (2008)
Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC (2007)
Alexandre Valentian, Edith Beigné
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction. ESSCIRC (2007)

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Publication Activity (10 Years)

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Edith Beigné