Motoi Ichihashi

Publication Activity (10 Years)

Years Active: 2006-2020
Publications (10 Years): 6

Top Topics

Metal Oxide Semiconductor

Application Specific

Top Venues

Publications

Motoi Ichihashi, Jia Zeng, Youngtag Woo, Xuelian Zhu, Chenchen Wang, James Mazza
Performance Boost Scheme with Activated Dummy Fin in 12-nm FinFET Technology for High-Performance Logic Application. ISQED (2020)
Motoi Ichihashi, Youngtag Woo, Muhammed Ahosan Ul Karim, Vivek Joshi, David Burnett
10T Differential-Signal SRAM Design in a L4-NM FinFET Technology for High-Speed Application. SoCC (2018)
Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye
Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. SoCC (2016)
Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim
How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions. ISLPED (2016)
Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz
On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs. ISVLSI (2016)
Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim
Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs. ICCAD (2016)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6 (1) (2010)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS (2009)
Motoi Ichihashi, Haruki Toda
Performance Measurement and Improvement of Asymmetric Three-Tr. Cell (ATC) DRAM toward 0.3V Memory Array Operation. VLSI Design (2006)
Koichiro Ishibashi, Tetsuya Fujimoto, Takahiro Yamashita, Hiroyuki Okada, Yukio Arima, Yasuyuki Hashimoto, Kohji Sakata, Isao Minematsu, Yasuo Itoh, Haruki Toda, Motoi Ichihashi, Yoshihide Komatsu, Masato Hagiwara, Toshiro Tsukada
Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond. IEICE Trans. Electron. (3) (2006)