Marc Belleville

Publication Activity (10 Years)

Years Active: 2007-2017
Publications (10 Years): 3

Top Topics

Cmos Technology

Top Venues

J. Low Power Electron.

Publications

Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. 13 (3) (2017)
Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville
Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. 57 (2016)
Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits. RC (2015)
Soundous Chairat, Edith Beigné, Marc Belleville
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS (2015)
Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. 10 (1) (2014)
Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS (2014)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI (2013)
Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. ICICDT (2013)
Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE (2013)
Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
Computing detection probability of delay defects in signal line tsvs. ETS (2013)
Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT (2013)
Marc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy
Design challenges for nano-scale devices. ESSDERC (2012)
Nadine Azémard, Marc Belleville
Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. 8 (1) (2012)
Dimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. ICICDT (2012)
J. Mazurier, Olivier Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, Jean-Philippe Noel, Marc Belleville, Olivier Faynot, T. Poiroux
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. J. Low Power Electron. 8 (1) (2012)
Florent Dupont, Cyril Condemine, Jean-François Beche, Marc Belleville
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring. ICECS (2012)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42 (5) (2011)
Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC (2011)
Marc Belleville, Hervé Fanet, Paolo Fiorini, Pierre Nicole, Marcel J. M. Pelgrom, Christian Piguet, Robert Hahn, Chris Van Hoof, Ruud J. M. Vullers, Marco Tartagni, Eugenio Cantatore
Energy autonomous sensor systems: Towards a ubiquitous sensor technology. Microelectron. J. 41 (11) (2010)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6 (1) (2010)
Marc Belleville
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. PATMOS (2010)
Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS (2009)
Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS (2009)
Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI (2008)
Olivier Thomas, Marina Reyboz, Marc Belleville
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. ISCAS (2007)