Yuanqing Cheng

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 39

Top Topics

Integrated Circuit

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Wei W. Xing, Longze Wang, Zhelong Wang, Zhaoyu Shi, Ning Xu, Yuanqing Cheng, Weisheng Zhao
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Hang Wu, Ning Xu, Wei W. Xing, Yuanqing Cheng
BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization. ASPDAC (2024)
Xinmiao Zhang, Cheng Liu, Jiacheng Ni, Yuanqing Cheng, Lei Zhang, Huawei Li, Xiaowei Li
PDG: A Prefetcher for Dynamic Graph Updating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Wei W. Xing, Zheng Xing, Rongqi Lu, Zhelong Wang, Ning Xu, Yuanqing Cheng, Weisheng Zhao
TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning. DAC (2023)
Yanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang, Wei W. Xing
OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. ICCAD (2023)
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30 (4) (2022)
Kangwei Xu, Yuanqing Cheng
Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs. ASP-DAC (2022)
Yuanqing Cheng, Xiaochen Guo, Vasilis F. Pavlidis
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective. Integr. 85 (2022)
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30 (4) (2022)
Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. ICCAD (2022)
Baoli Peng, Vasilis F. Pavlidis, Yi-Chung Chen, Yuanqing Cheng
Thermal Modeling and Design Exploration for Monolithic 3D ICs. ISQED (2022)
Kangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits. ACM J. Emerg. Technol. Comput. Syst. 18 (4) (2022)
Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Dawen Xu, Zhuangyu Feng, Cheng Liu, Li Li, Ying Wang, Yuanqing Cheng, Huawei Li, Xiaowei Li
Taming Process Variations in CNFET for Efficient Last Level Cache Design. CoRR (2021)
Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109 (2) (2021)
Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard, Yuanqing Cheng
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ISQED (2020)
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization. ACM J. Emerg. Technol. Comput. Syst. 16 (3) (2020)
Jiacheng Ni, Xiaochen Guo, Yuanqing Cheng
SIP: Boosting Up Graph Computing by Separating the Irregular Property Data. ACM Great Lakes Symposium on VLSI (2020)
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (4) (2020)
Wei Wang, Vasilis F. Pavlidis, Yuanqing Cheng
Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum Wirelength. ACM Great Lakes Symposium on VLSI (2020)
Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Chen Liu, Yuanqing Cheng, Ying Wang, Youguang Zhang, Weisheng Zhao
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs. ISCAS (2018)
Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization. ISVLSI (2018)
Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. J. Comput. Sci. Technol. 33 (5) (2018)
Linuo Xue, Bi Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy J. Kan, Seung H. Kang, Yuan Xie
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. ICCAD (2017)
Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie
Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC (2017)
Lili Song, Ying Wang, Yinhe Han, Huawei Li, Yuanqing Cheng, Xiaowei Li
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, Yuan Xie
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC (2016)
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Trans. Reliab. 65 (4) (2016)
Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM. IEEE Trans. Very Large Scale Integr. Syst. 24 (5) (2016)
Aida Todri-Sanial, Yuanqing Cheng
A Study of 3-D Power Delivery Networks With Multiple Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Liang Wu, Xiaoxiao Wang, Xiaoying Zhao, Yuanqing Cheng, Donglin Su, Aixin Chen, Qihang Shi, Mark M. Tehranipoor
AES design improvement towards information safety. ISCAS (2016)
Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie
ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. ICCAD (2016)
Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao
Quantitative evaluation of reliability and performance for STT-MRAM. ISCAS (2016)
Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark M. Tehranipoor
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC. ISCAS (2016)
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, Aida Todri-Sanial
A body-biasing of readout circuit for STT-RAM with improved thermal reliability. ISCAS (2015)
Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. ISVLSI (2015)
Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. NANOARCH (2015)
Ying Wang, Lili Song, Yinhe Han, Yuanqing Cheng, Huawei Li, Xiaowei Li
A case of precision-tunable STT-RAM memory design for approximate neural network. ISCAS (2015)
Jun Zhou, Huawei Li, Yuntan Fang, Tiancheng Wang, Yuanqing Cheng, Xiaowei Li
HARS: A High-Performance Reliable Routing Scheme for 3D NoCs. ISVLSI (2014)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC (2014)
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
TSV Minimization for Circuit - Partitioned 3D SoC Test Wrapper Design. J. Comput. Sci. Technol. 28 (1) (2013)
Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. 21 (2) (2013)
Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI (2013)
Yuanqing Cheng, Lei Zhang, Yinhe Han, Jun Liu, Xiaowei Li
Wrapper Chain Design for Testing TSVs Minimization in Circuit-Partitioned 3D SoC. Asian Test Symposium (2011)