Peter Debacker

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 33

Top Topics

Instance Based Learning Algorithms

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Giuseppe M. Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. CoRR (2024)
Mohit Gupta, Stefan Cosemans, Peter Debacker, Wim Dehaene
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. ESSCIRC (2023)
Subhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar
Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. IMW (2023)
Swatilekha Majumdar, Stefan Cosemans, Arindam Mallik, Peter Debacker, Francky Catthoor, Jan Van Houdt
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. ISCAS (2023)
Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits 58 (1) (2023)
Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. IISWC (2023)
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30 (4) (2022)
Simei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Nathan Laubeuf, Jonas Doevenspeck, Ioannis A. Papistas, Michele Caselli, Stefan Cosemans, Peter Vrancx, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Francky Catthoor, Rudy Lauwereins
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. ACM Trans. Design Autom. Electr. Syst. 27 (5) (2022)
Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni, Peter Debacker, Asen Asenov, Aida Todri-Sanial
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. IEEE Trans. Very Large Scale Integr. Syst. 30 (4) (2022)
Michele Caselli, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest
Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. ISCAS (2022)
Nitish Satya Murthy, Peter Vrancx, Nathan Laubeuf, Peter Debacker, Francky Catthoor, Marian Verhelst
Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge. SEC (2022)
Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe M. Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian P. Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC (2022)
Michele Caselli, Subhali Subhechha, Peter Debacker, Arindam Mallik, Diederik Verkest
Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing. ISCAS (2022)
Michele Caselli, Peter Debacker, Andrea Boni
Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications. IEEE Trans. Circuits Syst. II Express Briefs 69 (7) (2022)
Michele Caselli, Ioannis A. Papistas, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest
Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. NEWCAS (2021)
Debjyoti Bhattacharjee, Nathan Laubeuf, Stefan Cosemans, Ioannis A. Papistas, Arindam Mallik, Peter Debacker, Myung Hee Na, Diederik Verkest
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. ISCAS (2021)
Jonas Doevenspeck, Peter Vrancx, Nathan Laubeuf, Arindam Mallik, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene
Noise tolerant ternary weight deep neural networks for analog in-memory inference. IJCNN (2021)
Ioannis A. Papistas, Stefan Cosemans, Bram Rooseleer, Jonas Doevenspeck, Myung Hee Na, Arindam Mallik, Peter Debacker, Diederik Verkest
in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. CICC (2021)
Giuliano Sisto, Peter Debacker, Rongmei Chen, Geert Van der Plas, Richard Chou, Eric Beyne, Dragomir Milojevic
Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. 3DIC (2019)
Bram-Ernst Verhoef, Nathan Laubeuf, Stefan Cosemans, Peter Debacker, Ioannis A. Papistas, Arindam Mallik, Diederik Verkest
FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. CoRR (2019)
Jonas Doevenspeck, Robin Degraeve, Andrea Fantini, Peter Debacker, Diederik Verkest, Rudy Lauwereins, Wim Dehaene
Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. IRPS (2019)
Timon Evenblij, Christian Tenllado, Manu Perumkunnil, Francky Catthoor, Sushil Sakhare, Peter Debacker, Gouri Sankar Kar, Arnaud Furnémont, Nicolas Bueno, José Ignacio Gómez Pérez
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. ICCD (2019)
Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. AICAS (2019)
Luca Mattii, Dragomir Milojevic, Peter Debacker, Yasser Sherazi, Mladen Berekovic, Praveen Raghavan
IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. ICCAD (2017)
Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD (2017)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC (2017)
Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre
Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications. J. Signal Process. Syst. 84 (3) (2016)
Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI (2016)
Praveen Raghavan, Marie Garcia Bardon, Peter Debacker, P. Schuddinck, Doyoung Jang, Rogier Baert, Diederik Verkest, Aaron Voon-Yew Thean
5nm: Has the time for a device change come? ISQED (2016)
Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Diederik Verkest, Aaron Thean, Sung Kyu Lim
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. ISLPED (2016)
Bon Woong Ku, Peter Debacker, Dragomir Milojevic, Praveen Raghavan, Sung Kyu Lim
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? ICCAD (2016)
Meng Li, Jan-Willem Weijers, Veerle Derudder, Ilse Vos, Maxim Rykunov, Steven Dupont, Peter Debacker, Andy Dewilde, Yanxiang Huang, Liesbet Van der Perre, Wim Van Thillo
An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. A-SSCC (2015)
Yanxiang Huang, Meng Li, Chunshu Li, Peter Debacker, Liesbet Van der Perre
Computation-skip error resilient scheme for recursive CORDIC. SiPS (2014)
Meng Li, Frederik Naessens, Peter Debacker, Praveen Raghavan, Claude Desset, Min Li, Antoine Dejonghe, Liesbet Van der Perre
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard. SiPS (2013)
Meng Li, Frederik Naessens, Min Li, Peter Debacker, Claude Desset, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication. GlobalSIP (2013)
Min Li, Amir Amin, Raf Appeltans, Andy Folens, Ubaid Ahmad, Hans Cappelle, Peter Debacker, Lieven Hollevoet, André Bourdoux, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre
A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited). GlobalSIP (2013)
Martin Palkovic, Peter Debacker, Prabhat Avasare, Steven Dupont, Tom Vander Aa
Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. J. Low Power Electron. 8 (5) (2012)
Huub Tubbax, Johan Wouters, Jan Olbrechts, Peter Debacker, Peter Spiessens, Frederic Stubbe, Johan Danneels
A novel positioning technique for the 2.4GHz ISM band. WPNC (2009)