Vinay B. Y. Kumar

Publication Activity (10 Years)

Years Active: 2009-2022
Publications (10 Years): 12

Top Topics

Design Space Exploration

Fault Tolerance

Security Issues

Top Venues

IACR Cryptol. ePrint Arch.

Publications

Simei Yang, Debjyoti Bhattacharjee, Vinay B. Y. Kumar, Saikat Chatterjee, Sayandip De, Peter Debacker, Diederik Verkest, Arindam Mallik, Francky Catthoor
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (2) (2022)
Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks. DATE (2021)
Vinay B. Y. Kumar, Suman Deb, Naina Gupta, Shivam Bhasin, Jawad Haj-Yahya, Anupam Chattopadhyay, Avi Mendelson
Towards Designing a Secure RISC-V System-on-Chip: ITUS. J. Hardw. Syst. Secur. 4 (4) (2020)
Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay
A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis. ACISP (2020)
Vinay B. Y. Kumar, Naina Gupta, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß, Ruben Niederhagen
Post-Quantum Secure Boot. DATE (2020)
Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks (Extended Version). IACR Cryptol. ePrint Arch. 2020 (2020)
Shivam Bhasin, Trevor E. Carlson, Anupam Chattopadhyay, Vinay B. Y. Kumar, Avi Mendelson, Romain Poussier, Yaswanth Tavva
Secure Your SoC: Building System-an-Chip Designs for Security. SoCC (2020)
Anubhab Baksi, Vinay B. Y. Kumar, Banashri Karmakar, Shivam Bhasin, Dhiman Saha, Anupam Chattopadhyay
A Novel Duplication Based Countermeasure To Statistical Ineffective Fault Analysis. IACR Cryptol. ePrint Arch. 2020 (2020)
Vinay B. Y. Kumar, Suman Deb, Rupesh Kumar, Mustafa Khairallah, Anupam Chattopadhyay, Avi Mendelson
Recruiting Fault Tolerance Techniques for Microprocessor Security. ATS (2019)
Vinay B. Y. Kumar, Anupam Chattopadhyay, Jawad Haj-Yahya, Avi Mendelson
ITUS: A Secure RISC-V System-on-Chip. SoCC (2019)
Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar
Lightweight Forth Programmable NoCs. VLSI Design (2018)
Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. VLSI Design (2016)
Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies. CoRR (2015)
Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar
Parallel two step random walk algorithm to analyze VLSI power grid networks. VDAT (2015)
Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. ICCD (2014)
Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. VLSI-DAT (2014)
Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar
FPGA-based implementation of M4RM for matrix multiplication over GF(2). VDAT (2014)
Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. PECCS (2013)
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
FPGA Based High Performance Double-Precision Matrix Multiplication. Int. J. Parallel Program. 38 (3-4) (2010)
Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan
FPGA Based High Performance Double-Precision Matrix Multiplication. VLSI Design (2009)