An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS.
Meng LiJan-Willem WeijersVeerle DerudderIlse VosMaxim RykunovSteven DupontPeter DebackerAndy DewildeYanxiang HuangLiesbet Van der PerreWim Van ThilloPublished in: A-SSCC (2015)
Keyphrases
- low density parity check
- silicon on insulator
- ldpc codes
- ibm power processor
- error resilience
- high speed
- decoding algorithm
- low power
- cmos technology
- single chip
- nm technology
- error correction
- wireless sensor networks
- turbo codes
- parallel processing
- channel coding
- power consumption
- distributed video coding
- random access memory
- metal oxide semiconductor
- energy efficient
- message passing
- source coding
- dynamic random access memory
- low cost
- energy efficiency
- chip design
- error propagation
- xilinx virtex
- physical layer
- sensor networks
- mac protocol
- error detection
- bitstream
- low voltage
- integrated circuit
- packet loss
- video codec
- image transmission
- video transmission
- coding scheme
- video coding
- clock frequency
- error concealment
- image sensor
- rate allocation