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Bram Rooseleer
Publication Activity (10 Years)
Years Active: 2010-2021
Publications (10 Years): 1
Top Topics
Memory Usage
Transformation Matrix
Top Venues
CICC
ESSCIRC
IEEE J. Solid State Circuits
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Publications
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Ioannis A. Papistas
,
Stefan Cosemans
,
Bram Rooseleer
,
Jonas Doevenspeck
,
Myung Hee Na
,
Arindam Mallik
,
Peter Debacker
,
Diederik Verkest
in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration.
CICC
(2021)
Bram Rooseleer
,
Wim Dehaene
A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump.
ESSCIRC
(2013)
Bram Rooseleer
,
Stefan Cosemans
,
Wim Dehaene
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link.
IEEE J. Solid State Circuits
47 (7) (2012)
Bram Rooseleer
,
Stefan Cosemans
,
Wim Dehaene
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link.
ESSCIRC
(2011)
Pavel Poliakov
,
Ankur Anchlia
,
Marie Garcia Bardon
,
Bram Rooseleer
,
Bart De Wachter
,
Nadine Collaert
,
Koen van der Zanden
,
Wim Dehaene
,
Diederik Verkest
,
Miguel Corbalan Miranda
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM.
IEEE Trans. Circuits Syst. II Express Briefs
(3) (2010)