Kwangsoo Han

Publication Activity (10 Years)

Years Active: 2014-2020
Publications (10 Years): 10

Top Topics

Optimization Process

Shortest Path Routing

Advanced Technology

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Kwangsoo Han, Andrew B. Kahng, Jiajia Li
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. SLIP@DAC (2018)
Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD (2018)
Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng
Benchmarking of Mask Fracturing Heuristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (1) (2017)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD (2017)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED (2017)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC (2017)
Kwangsoo Han, Andrew B. Kahng, Jiajia Li
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE (2016)
Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. ASP-DAC (2016)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC (2015)
Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas
Clock clustering and IO optimization for 3D integration. SLIP (2015)
Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC (2015)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD (2015)
Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI (2014)
Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria
Benchmarking of mask fracturing heuristics. ICCAD (2014)