Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.
Kwangsoo HanAndrew B. KahngJiajia LiPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
Keyphrases
- low power
- power consumption
- high speed
- low power consumption
- low cost
- signal processor
- digital signal processing
- single chip
- wireless transmission
- logic circuits
- vlsi architecture
- power reduction
- high power
- cmos technology
- image sensor
- index structure
- mixed signal
- vlsi circuits
- b tree
- model checking
- real time
- wireless sensor networks