Jiajia Li

Publication Activity (10 Years)

Years Active: 2013-2020
Publications (10 Years): 18

Top Topics

Power Reduction

Addressing These Issues

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Kwangsoo Han, Andrew B. Kahng, Jiajia Li
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66 (2019)
Sorin Dobre, Andrew B. Kahng, Jiajia Li
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (4) (2018)
Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (7) (2018)
Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC (2017)
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 13 (3) (2017)
Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
Revisiting 3DIC benefit with multiple tiers. Integr. 58 (2017)
Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Andrew B. Kahng, Jiajia Li, Lutong Wang
Improved flop tray-based design implementation for power reduction. ICCAD (2016)
Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li
Revisiting 3DIC Benefit with Multiple Tiers. SLIP (2016)
Kwangsoo Han, Andrew B. Kahng, Jiajia Li
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE (2016)
Andrew B. Kahng, Hyein Lee, Jiajia Li
Measuring progress and value of IC implementation technology. ICCAD (2016)
Kun Young Chung, Andrew B. Kahng, Jiajia Li
Comprehensive optimization of scan chain timing during late-stage IC implementation. DAC (2016)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Sorin Dobre, Andrew B. Kahng, Jiajia Li
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. ICCAD (2015)
Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD (2015)
Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC (2015)
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. ISQED (2014)
Andrew B. Kahng, Hyein Lee, Jiajia Li
Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI (2014)
Andrew B. Kahng, Seokhyeong Kang, Jiajia Li
A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI (2014)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
Reliability-constrained die stacking order in 3DICs under manufacturing variability. ISQED (2013)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath
Optimization of overdrive signoff. ASP-DAC (2013)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li
Toward quantifying the IC design value of interconnect technology improvements. SLIP (2013)