Siddhartha Nath

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 13

Top Topics

Special Session

Reinforcement Learning

Machine Learning

Top Venues

Publications

Yi-Chen Lu, Siddhartha Nath, Sai Pentapati, Sung Kyu Lim
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation. ACM Trans. Design Autom. Electr. Syst. 28 (4) (2023)
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren
BufFormer: A Generative ML Framework for Scalable Buffering. ASP-DAC (2023)
Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu
Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). ICCAD (2022)
Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
TransSizer: A Novel Transformer-Based Fast Gate Sizer. ICCAD (2022)
Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren
Generative self-supervised learning for gate sizing: invited. DAC (2022)
Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph Learning. ICCAD (2021)
Siddhartha Nath, Vishal Khandelwal
Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes. ISPD (2021)
Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy
Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper. ICCAD (2021)
Yi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim
RL-Sizer: VLSI Gate Sizing for Timing Optimization using Deep Reinforcement Learning. DAC (2021)
Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim
A Fast Learning-Driven Signoff Power Optimization Framework. ICCAD (2020)
Prabhav Agrawal, Mike Broxterman, Biswadeep Chatterjee, Patrick Cuevas, Kathy H. Hayashi, Andrew B. Kahng, Pranay K. Myana, Siddhartha Nath
Optimal Scheduling and Allocation for IC Design Management and Cost Reduction. ACM Trans. Design Autom. Electr. Syst. 22 (4) (2017)
Wei-Ting Jonas Chan, Yang Du, Andrew B. Kahng, Siddhartha Nath, Kambiz Samadi
BEOL stack-aware routability prediction from placement using data mining techniques. ICCD (2016)
Wei-Ting Jonas Chan, Kun Young Chung, Andrew B. Kahng, Nancy D. MacDonald, Siddhartha Nath
Learning-based prediction of embedded memory timing failures during initial floorplan design. ASP-DAC (2016)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Andrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins
Toward Metrics of Design Automation Research Impact. ICCAD (2015)
Wei-Ting Jonas Chan, Siddhartha Nath, Andrew B. Kahng, Yang Du, Kambiz Samadi
3DIC benefit estimation and implementation guidance from 2DIC implementation. DAC (2015)
Andrew B. Kahng, Mulong Luo, Siddhartha Nath
SI for free: machine learning of interconnect coupling delay and transition effects. SLIP (2015)
Andrew B. Kahng, Bill Lin, Siddhartha Nath
ORION3.0: A Comprehensive NoC Router Estimation Tool. IEEE Embed. Syst. Lett. 7 (2) (2015)
Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC (2015)
Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath
Methodology for electromigration signoff in the presence of adaptive voltage scaling. SLIP (2014)
Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath, Ichiro Yamamoto
The ITRS MPU and SOC system drivers: Calibration and implications for design-based equivalent scaling in the roadmap. ICCD (2014)
Juan Antonio Carballo, Wei-Ting Jonas Chan, Paolo A. Gargini, Andrew B. Kahng, Siddhartha Nath
ITRS 2.0: Toward a re-framing of the Semiconductor Technology Roadmap. ICCD (2014)
Andrew B. Kahng, Siddhartha Nath
Optimal reliability-constrained overdrive frequency selection in multicore systems. ISQED (2014)
Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI (2014)
Seung-Soo Han, Andrew B. Kahng, Siddhartha Nath, Ashok S. Vydyanathan
A deep learning methodology to proliferate golden signoff timing. DATE (2014)
Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath
Optimization of overdrive signoff. ASP-DAC (2013)
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP (2013)
Andrew B. Kahng, Ilgweon Kang, Siddhartha Nath
Incremental multiple-scan chain ordering for ECO flip-flop insertion. ICCAD (2013)
Andrew B. Kahng, Siddhartha Nath, Tajana Rosing
On potential design impacts of electromigration awareness. ASP-DAC (2013)
Andrew B. Kahng, Bill Lin, Siddhartha Nath
High-dimensional metamodeling for prediction of clock tree synthesis outcomes. SLIP (2013)
Andrew B. Kahng, Bill Lin, Siddhartha Nath
Enhanced metamodeling techniques for high-dimensional IC design estimation problems. DATE (2013)
Andrew B. Kahng, Bill Lin, Siddhartha Nath
Explicit modeling of control and data for improved NoC router estimation. DAC (2012)
Manish Arora, Siddhartha Nath, Subhra Mazumdar, Scott B. Baden, Dean M. Tullsen
Redefining the Role of the CPU in the Era of CPU-GPU Integration. IEEE Micro 32 (6) (2012)
Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Vikram Bhatt, Jonathan Babb, Steven Swanson, Michael B. Taylor
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future. IEEE Micro 31 (2) (2011)