Hyein Lee

Publication Activity (10 Years)

Years Active: 2013-2020
Publications (10 Years): 10

Top Topics

Power Reduction

Heuristic Methods

Advanced Technology

Total Hip Arthroplasty

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Hamed Fatemi, Andrew B. Kahng, Hyein Lee, José Pineda de Gyvez
Heuristic Methods for Fine-Grain Exploitation of FDSOI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66 (2019)
Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (7) (2018)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD (2017)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED (2017)
Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC (2017)
Andrew B. Kahng, Hyein Lee, Jiajia Li
Measuring progress and value of IC implementation technology. ICCAD (2016)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC (2015)
Kwangsoo Han, Andrew B. Kahng, Hyein Lee
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD (2015)
Andrew B. Kahng, Hyein Lee, Jiajia Li
Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI (2014)
Andrew B. Kahng, Hyein Lee
Minimum implant area-aware gate sizing and placement. ACM Great Lakes Symposium on VLSI (2014)
Andrew B. Kahng, Hyein Lee
Timing margin recovery with flexible flip-flop timing model. ISQED (2014)
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar
High-performance gate sizing with a signoff timer. ICCAD (2013)
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Siddhartha Nath, Jyoti Wadhwani
Learning-based approximation of interconnect delay and slew in signoff timing tools. SLIP (2013)
Andrew B. Kahng, Seokhyeong Kang, Hyein Lee
Smart non-default routing for clock power reduction. DAC (2013)