Anand Rajaram

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 2

Top Topics

Evolutionary Algorithm

Cognitive Science

Framework Enables

Feature Selection

Top Venues

Publications

Anthony Agnesina, Rongjian Liang, Geraldo Pradipta, Anand Rajaram, Haoxing Ren
GOALPlace: Begin with the End in Mind. CoRR (2024)
Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren
BufFormer: A Generative ML Framework for Scalable Buffering. ASP-DAC (2023)
Anand Rajaram, David Z. Pan
Robust Chip-Level Clock Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (6) (2011)
Anand Rajaram, David Z. Pan
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE (2009)
Anand Rajaram, David Z. Pan
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC (2008)
Anand Rajaram, Raguram Damodaran, Arjun Rajagopal
Practical Clock Tree Robustness Signoff Metrics. ISQED (2008)
Anand Rajaram, David Z. Pan
Robust chip-level clock tree synthesis for SOC designs. DAC (2008)
Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. ISSCC (2007)
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED (2007)
Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
Reducing clock skew variability via crosslinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Anand Rajaram, David Z. Pan
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED (2006)
Anand Rajaram, David Z. Pan
Variation tolerant buffered clock network synthesis with cross links. ISPD (2006)
Anand Rajaram, David Z. Pan, Jiang Hu
Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD (2005)
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD (2005)
Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
Reducing clock skew variability via cross links. DAC (2004)
Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD (2003)