Ashutosh Chakraborty

Publication Activity (10 Years)

Years Active: 2003-2013
Publications (10 Years): 0

Top Topics

Database Administrators

Application Layer

Physical Design

Packet Forwarding

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Ashutosh Chakraborty, David Z. Pan
Skew Management of NBTI Impacted Gated Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (6) (2013)
Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni De Micheli
Cell transformations and physical design techniques for 3D monolithic integrated circuits. ACM J. Emerg. Technol. Comput. Syst. 9 (3) (2013)
Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan
Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction. ICCAD (2012)
Ashutosh Chakraborty, David Z. Pan
Controlling NBTI degradation during static burn-in testing. ASP-DAC (2011)
Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli
CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits. ASP-DAC (2011)
Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD (2010)
Ashutosh Chakraborty, David Z. Pan
Skew management of NBTI impacted gated clock trees. ISPD (2010)
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (10) (2010)
Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli
Performance analysis of 3-D monolithic integrated circuits. 3DIC (2010)
Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2010)
Ashutosh Chakraborty, David Z. Pan
PASAP: power aware structured ASIC placement. ISLPED (2010)
Ashutosh Chakraborty, Anurag Kumar, David Z. Pan
RegPlace: a high quality open-source placement framework for structured ASICs. DAC (2009)
Ashutosh Chakraborty, David Z. Pan
On stress aware active area sizing, gate sizing, and repeater insertion. ISPD (2009)
Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE (2009)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integr. 41 (1) (2008)
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan
An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC (2008)
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE (2008)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS (2006)
Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal resilient bounded-skew clock tree optimization methodology. DATE (2006)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS (2006)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED (2006)
Ashutosh Chakraborty, Enrico Macii, Massimo Poncino
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding. PATMOS (2005)
Pradeep Varma, Ashutosh Chakraborty
Low-Voltage, Double-Edge-Triggered Flip Flop. PATMOS (2003)