Ashoka Visweswara Sathanur

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Optimization Methods

High Level Synthesis

Top Venues

Microelectron. J.

Publications

Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini
Row-based FBB: A design-time optimization for post-silicon tunable circuits. Microelectron. J. 43 (7) (2012)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19 (3) (2011)
Antonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications. VLSI-SoC (2011)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Ashoka Visweswara Sathanur, Jos Huisken, Jan Stuyt, Harmke de Groot
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs. ICECS (2010)
Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini
Automatic synthesis of near-threshold circuits with fine-grained performance tunability. ISLPED (2010)
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii
Physically clustered forward body biasing for variability compensation in nanometer CMOS design. DATE (2009)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating. J. Low Power Electron. 5 (1) (2009)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations. Integr. 41 (1) (2008)
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI (2008)
Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS (2008)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. PATMOS (2008)
Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. ISLPED (2008)
Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4 (3) (2008)
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE (2008)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. ISCAS (2007)
Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. DATE (2007)
Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Timing-driven row-based power gating. ISLPED (2007)
Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI (2007)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. ISCAS (2006)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. PATMOS (2006)
Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic thermal clock skew compensation using tunable delay buffers. ISLPED (2006)