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Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.

Ashoka Visweswara SathanurLuca BeniniAlberto MaciiEnrico MaciiMassimo Poncino
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
  • power consumption
  • power dissipation
  • high speed
  • low power
  • chip design
  • circuit design
  • design methodology
  • power reduction
  • vlsi circuits
  • global optimization
  • power management
  • genetic algorithm
  • power losses