R. Iris Bahar

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 45

Top Venues

Publications

Samuel Thomas, Kidus Workneh, Ange-Thierry Ishimwe, Zack McKevitt, Phaedra S. Curlin, R. Iris Bahar, Joseph Izraelevitz, Tamara Lehman
Baobab Merkle Tree for Efficient Secure Memory. IEEE Comput. Archit. Lett. 23 (1) (2024)
Samuel Thomas, Kidus Workneh, Jac McCarty, Joseph Izraelevitz, Tamara Lehman, R. Iris Bahar
A Midsummer Night's Tree: Efficient and High Performance Secure SCM. ASPLOS (3) (2024)
Semanti Basu, Peter Bajcsy, Thomas E. Cleveland IV, Manuel J. Carrasco, R. Iris Bahar
LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation. BIOIMAGING (2023)
Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. SPAA (2022)
Yanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar
A Reconfigurable Hardware Library for Robot Scene Perception. ICCAD (2022)
Casey Nelson, Joseph Izraelevitz, R. Iris Bahar, Tamara Silbergleit Lehman
Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing. SEED (2022)
R. Iris Bahar
EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing. IPDPS Workshops (2022)
Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. HPEC (2022)
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC (2021)
Semir Tatlidil, Yanqi Liu, Emily Sheetz, R. Iris Bahar, Steven A. Sloman
Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning. CoRR (2021)
Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar
Hardware Acceleration of Robot Scene Perception Algorithms. ICCAD (2020)
Yanqi Liu, Giuseppe Calderoni, R. Iris Bahar
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. CoRR (2020)
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
Voltage Noise Mitigation With Barrier Approximation. IEEE Comput. Archit. Lett. 19 (2) (2020)
R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond. CoRR (2020)
Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. SPAA (2019)
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. IISWC (2019)
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Test Architecture for Fine Grained Capture Power Reduction. ICECS (2019)
R. Iris Bahar
Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018). IEEE Des. Test 36 (2) (2019)
R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic
Special Session: Does Approximation Make Testing Harder (or Easier)? VTS (2019)
Kumud Nepal, Soheil Hashemi, Hokchhay Tann, R. Iris Bahar, Sherief Reda
Automated High-Level Generation of Low-Power Approximate Computing Circuits. IEEE Trans. Emerg. Top. Comput. 7 (1) (2019)
Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. IROS (2019)
Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. CoRR (2019)
Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35 (6) (2019)
Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. DATE (2019)
Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Attacking memory-hard scrypt with near-data-processing. MEMSYS (2019)
Christopher B. Harris, R. Iris Bahar
Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems. J. Low Power Electron. 14 (1) (2018)
Sri Parameswaran, R. Iris Bahar, David Z. Pan
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test 35 (2) (2018)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. Int. J. Parallel Program. 46 (6) (2018)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Yanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins
Robust object estimation using generative-discriminative inference for secure robotics applications. ICCAD (2018)
Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar
Evaluating critical bits in arithmetic operations due to timing violations. HPEC (2017)
Christopher B. Picardo, Justin G. R. Delva, R. Iris Bahar
Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps. MWSCAS (2017)
Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
Understanding the impact of precision quantization on the accuracy and energy of neural networks. DATE (2017)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. ACM Trans. Embed. Comput. Syst. 16 (5s) (2017)
Christopher B. Harris, R. Iris Bahar
A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots. NGCAS (2017)
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. DAC (2017)
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. CoRR (2016)
Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. ACM Great Lakes Symposium on VLSI (2016)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A fast simulator for the analysis of sub-threshold thermal noise transients. DAC (2016)
Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW (2016)
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
Runtime configurable deep neural networks for energy-accuracy trade-off. CODES+ISSS (2016)
Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. FPL (2016)
Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. CASES (2016)
Soheil Hashemi, R. Iris Bahar, Sherief Reda
A low-power dynamic divider for approximate applications. DAC (2016)
Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. CoRR (2016)
Soheil Hashemi, R. Iris Bahar, Sherief Reda
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. ICCAD (2015)
Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
R. Iris Bahar, Alex K. Jones, Yuan Xie
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. ACM Great Lakes Symposium on VLSI (2015)
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. ACM Great Lakes Symposium on VLSI (2015)
Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. ACM Trans. Embed. Comput. Syst. 14 (3) (2015)
Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. DATE (2014)
Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. ACM Trans. Reconfigurable Technol. Syst. 7 (1) (2014)
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar
Speculative synchronization for coherence-free embedded NUMA architectures. ICSAMOS (2014)
R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov
"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation. MSE (2013)
Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar
Flexible data allocation for scratch-pad memories to reduce NBTI effects. ISQED (2013)
Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. MES (2013)
Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS (2013)
Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI (2012)
Roto Le, Joseph L. Mundy, R. Iris Bahar
High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. ASAP (2012)
Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. J. Electron. Test. 28 (3) (2012)
Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM (2012)
Roto Le, R. Iris Bahar, Joseph L. Mundy
A novel parallel Tier-1 coder for JPEG2000 using GPUs. SASP (2011)
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. CODES+ISSS (2011)
Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
NBTI-aware data allocation strategies for scratchpad memory based embedded systems. LATW (2011)
Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS (2011)
Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
Enhancing online error detection through area-efficient multi-site implications. VTS (2011)
Desta Tadesse, R. Iris Bahar, Joel Grodstein
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. J. Electron. Test. 27 (2) (2011)
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. J. Parallel Distributed Comput. 70 (10) (2010)
Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI (2010)
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI (2010)
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. IEEE Trans. Very Large Scale Integr. Syst. 18 (11) (2010)
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. HiPEAC (2010)
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
assignment policies in ITD-aware synthesis. Microelectron. J. 41 (9) (2010)
Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Sherief Reda, Aung Si, R. Iris Bahar
Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED (2009)
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
Compacting test vector sets via strategic use of implications. ICCAD (2009)
R. Iris Bahar
Introduction to special section: Best of NANOARCH 2008. ACM J. Emerg. Technol. Comput. Syst. 5 (2) (2009)
Roto Le, Sherief Reda, R. Iris Bahar
High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI (2009)
Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino
Energy-optimal synchronization primitives for single-chip multi-processors. ACM Great Lakes Symposium on VLSI (2009)
Roto Le, Sherief Reda, R. Iris Bahar
High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA (2009)
Desta Tadesse, Joel Grodstein, R. Iris Bahar
AutoRex: An automated post-silicon clock tuning tool. ITC (2009)
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Detecting errors using multi-cycle invariance information. DATE (2009)
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. ISLPED (2008)
Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
Energy efficient synchronization techniques for embedded architectures. ACM Great Lakes Symposium on VLSI (2008)
Cesare Ferri, Sherief Reda, R. Iris Bahar
Parametric yield management for 3D ICs: Models and strategies for improvement. ACM J. Emerg. Technol. Comput. Syst. 4 (4) (2008)
R. Iris Bahar, Krishnendu Chakrabarty
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. J. Low Power Electron. 4 (3) (2008)
Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar
Temperature-insensitive synthesis using multi-vt libraries. ACM Great Lakes Symposium on VLSI (2008)
R. Iris Bahar, Krishnendu Chakrabarty
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. ACM J. Emerg. Technol. Comput. Syst. 4 (2) (2008)
Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
Using Implications for Online Error Detection. ITC (2008)
Desta Tadesse, R. Iris Bahar, Joel Grodstein
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS (2008)
R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram
Architectures for Silicon Nanoelectronics and Beyond. Computer 40 (1) (2007)
Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar
Thermally-induced soft errors in nanoscale CMOS circuits. NANOARCH (2007)
Cesare Ferri, Sherief Reda, R. Iris Bahar
Strategies for improving the parametric yield and profits of 3D ICs. ICCAD (2007)
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy
A hardware/software framework for supporting transactional memory in a MPSoC environment. SIGARCH Comput. Archit. News 35 (1) (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE (2007)
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
Accurate timing analysis using SAT and pattern-dependent delay models. DATE (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23 (2-3) (2007)

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Publication Activity (10 Years)

Top Topics

Top Venues

R. Iris Bahar