Justin E. Harlow III

Publication Activity (10 Years)

Years Active: 1977-2007
Publications (10 Years): 0

Publications

R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram
Architectures for Silicon Nanoelectronics and Beyond. Computer 40 (1) (2007)
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
A novel approach for variation aware power minimization during gate sizing. ISLPED (2006)
Justin E. Harlow III
Toward Design Technology in 2020: Trends, Issues, and Challenges. ISVLSI (2003)
Justin E. Harlow III, Franc Brglez
Design of experiments and evaluation of BDD ordering heuristics. Int. J. Softw. Tools Technol. Transf. 3 (2) (2001)
Justin E. Harlow III
Overview of Popular Benchmark Sets. IEEE Des. Test Comput. 17 (3) (2000)
Scott Davidson, Justin E. Harlow III
Guest Editors' Introduction: Benchmarking for Design and Test. IEEE Des. Test Comput. 17 (3) (2000)
Justin E. Harlow III, Franc Brglez
Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) (1999)
Justin E. Harlow III, Franc Brglez
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD (1998)
Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE (1998)
Justin E. Harlow III, Franc Brglez
Design of experiments in BDD variable ordering: lessons learned. ICCAD (1998)
Justin E. Harlow III
The open shop interactive mask design operation at harris semiconductor. DAC (1977)