Venkataraman Mahalingam

Publication Activity (10 Years)

Years Active: 2003-2012
Publications (10 Years): 0

Top Topics

Signal Processing

Power Consumption

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

Publications

Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.
Dynamic clock stretching for variation compensation in VLSI circuit design. ACM J. Emerg. Technol. Comput. Syst. 8 (3) (2012)
Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. Very Large Scale Integr. Syst. 18 (1) (2010)
Venkataraman Mahalingam, N. Ranganathan
Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam
Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan
A VLSI System Architecture for Optical Flow Computation. ISCAS (2009)
Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI (2008)
Venkataraman Mahalingam, Nagarajan Ranganathan
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI (2008)
Venkataraman Mahalingam, N. Ranganathan
Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED (2007)
Venkataraman Mahalingam, Nagarajan Ranganathan
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55 (12) (2006)
Venkataraman Mahalingam, N. Ranganathan
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design (2006)
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
A novel approach for variation aware power minimization during gate sizing. ISLPED (2006)
Venkataraman Mahalingam, N. Ranganathan
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI (2005)
N. Venkateswaran, V. Barath Kumar, R. Raghavan, R. Srinivas, S. Subramanian, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design. DELTA (2004)
N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T. L. Rajaprabhu
Analysis of Bit Transition Count for EDAC Encoded FSM. IOLTS (2003)