N. Ranganathan

Publication Activity (10 Years)

Years Active: 1988-2011
Publications (10 Years): 0

Publications

Koustav Bhattacharya, N. Ranganathan
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Yue Wang, N. Ranganathan
An Instruction-Level Energy Estimation and Optimization Methodology for GPU. CIT (2011)
Himanshu Thapliyal, N. Ranganathan
A new reversible design of BCD adder. DATE (2011)
Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. Very Large Scale Integr. Syst. 18 (1) (2010)
Venkataraman Mahalingam, N. Ranganathan
Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan
A Strategy for Soft Error Reduction in Multi Core Designs. ISCAS (2009)
Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 16 (8) (2008)
N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam
Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI (2008)
Venkataraman Mahalingam, N. Ranganathan
Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED (2007)
Upavan Gupta, N. Ranganathan
Social Fairness in Multi-Emergency Resource Management. ISTAS (2006)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11 (1) (2006)
Venkataraman Mahalingam, N. Ranganathan
An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design (2006)
Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III
A novel approach for variation aware power minimization during gate sizing. ISLPED (2006)
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11 (3) (2006)
Saraju P. Mohanty, N. Ranganathan
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10 (2) (2005)
Venkataraman Mahalingam, N. Ranganathan
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI (2005)
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design (2005)
Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan
Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design (2005)
N. Ranganathan
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 12 (1) (2004)
Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan
Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognit. Lett. 25 (7) (2004)
Ashok K. Murugavel, N. Ranganathan
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design (2004)
Ashok K. Murugavel, N. Ranganathan
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design (2004)
Sanjukta Bhanja, N. Ranganathan
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Ashok K. Murugavel, N. Ranganathan
Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
N. Ranganathan, Ashok K. Murugavel
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD (2003)
N. Ranganathan, Ashok K. Murugavel
A low power scheduler using game theory. CODES+ISSS (2003)
Sanjukta Bhanja, N. Ranganathan
Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD (2003)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI (2003)
Ashok K. Murugavel, N. Ranganathan
A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design (2003)
Saraju P. Mohanty, N. Ranganathan
Energy Efficient Scheduling for Datapath Synthesis. VLSI Design (2003)
Saraju P. Mohanty, N. Ranganathan
A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design (2003)
Abdel Ejnioui, N. Ranganathan
Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 11 (1) (2003)
Abdel Ejnioui, N. Ranganathan
Routing on field-programmable switch matrices. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) (2003)
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
Peak Power Minimization Through Datapath Scheduling. ISVLSI (2003)
Ashok K. Murugavel, N. Ranganathan
A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11 (6) (2003)
Sanjukta Bhanja, N. Ranganathan
Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD (2002)
Ashok K. Murugavel, N. Ranganathan
A Real Delay Switching Activity Simulator Based on Petri Net Modeling. VLSI Design (2002)
Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna
Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI (2002)
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
Least-square estimation of average power in digital CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Ashok K. Murugavel, N. Ranganathan
Petri net modeling of gate and interconnect delays for power estimation. DAC (2002)
Hitoshi Oi, N. Ranganathan
A comparative study of bidirectional ring and crossbar interconnection networks. Comput. Electr. Eng. 28 (1) (2002)
Sanjukta Bhanja, N. Ranganathan
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. VLSI Design (2002)
Ashok K. Murugavel, N. Ranganathan
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED (2002)
K. Sitaraman, N. Ranganathan, Abdel Ejnioui
A VLSI Architecture for Object Recognition Using Tree Matching. ASAP (2002)
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design (2001)
Minesh I. Patel, N. Ranganathan
IDUTC: an intelligent decision-making system for urban traffic-control applications. IEEE Trans. Veh. Technol. 50 (3) (2001)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
Context-based lossless image coding using EZW framework. IEEE Trans. Circuits Syst. Video Technol. 11 (4) (2001)
Sanjukta Bhanja, N. Ranganathan
Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC (2001)
N. Ranganathan, Minesh I. Patel, R. Sathyamurthy
An intelligent system for failure detection and control in an autonomous underwater vehicle. IEEE Trans. Syst. Man Cybern. Part A 31 (6) (2001)
Abdel Ejnioui, N. Ranganathan
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan
CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. VLSI Design (2000)
Raju D. Venkataramana, N. Ranganathan
New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. Heterogeneous Computing Workshop (2000)
Abdel Ejnioui, N. Ranganathan
Design Partitioning on Single-Chip Emulation Systems. VLSI Design (2000)
Hitoshi Oi, N. Ranganathan
Utilization of cache area in on-chip multiprocessor. Microprocess. Microsystems 24 (8) (2000)
Abdel Ejnioui, N. Ranganathan
Routing on Switch Matrix Multi-FPGA Systems. VLSI Design (2000)
Hitoshi Oi, N. Ranganathan
Utilization of Cache Area in On-Chip Multiprocessor. ISHPC (1999)
Veeru N. Ramaswamy, N. Ranganathan, Kameswara Rao Namuduri
Performance analysis of wavelets in embedded zerotree-based lossless image coding schemes. IEEE Trans. Signal Process. 47 (3) (1999)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. ISCAS (4) (1999)
Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
Computation of lower bounds for switching activity using decision theory. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Abdel Ejnioui, N. Ranganathan
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA (1999)
Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
A tree-matching chip. IEEE Trans. Very Large Scale Integr. Syst. 7 (2) (1999)
Raju D. Venkataramana, N. Ranganathan
A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. SAC (1999)
Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design (1999)
Raju D. Venkataramana, N. Ranganathan
Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. Heterogeneous Computing Workshop (1999)
Ramamurti Chandramouli, N. Ranganathan
Computing the bivariate Gaussian probability integral. IEEE Signal Process. Lett. 6 (6) (1999)
Narayanan Vijaykrishnan, N. Ranganathan
Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS (1999)
Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss
Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. Data Compression Conference (1998)
Raghu Sastry, N. Ranganathan
A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47 (3) (1998)
Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan
Rate control for a video coder using learning automata. SMC (1998)
Girish Chiruvolu, Ravi Sankar, N. Ranganathan
Adaptive VBR video traffic management for higher utilization of ATM networks. Comput. Commun. Rev. 28 (3) (1998)
Vamsi Krishna, N. Ranganathan
A Methodology for High Level Power Estimation and Exploration. Great Lakes Symposium on VLSI (1998)
Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla
Object-Oriented Architectural Support for a Java Processor. ECOOP (1998)
Raju D. Venkataramana, N. Ranganathan
A simple adaptive wormhole routing algorithm for MIMD systems. ICCD (1998)
Ramamurti Chandramouli, N. Ranganathan
A generalized sequential sign detector for binary hypothesis testing. IEEE Signal Process. Lett. 5 (11) (1998)
Girish Chiruvolu, Tapas K. Das, Ravi Sankar, N. Ranganathan
A scene-based generalized Markov chain model for VBR video traffic. ICC (1998)
Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan
Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. ICIP (1) (1998)
Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan
Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. VLSI Design (1998)
N. Ranganathan
A Forum for VLSI Practitioners. Computer 31 (10) (1998)
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan
SMAC: A VLSI Architecture for Scene Matching. Real Time Imaging 4 (3) (1998)
Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss
Adaptive quantization and fast error-resilient entropy coding for image transmission. IEEE Trans. Circuits Syst. Video Technol. 8 (4) (1998)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. ICIP (2) (1997)
Ashley Rasquinha, N. Ranganathan
C3L: A Chip for Connected Component Labeling. VLSI Design (1997)
Hitoshi Oi, N. Ranganathan
Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. ICCD (1997)
Minesh I. Patel, N. Ranganathan
An intelligent system architecture for urban traffic control applications. SPDP (1996)
S. Arumugavelu, N. Ranganathan
SIMD algorithms for single link and complete link pattern clustering. ICPR (1996)
S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri
A VLSI system architecture for lossless image compression. ICPR (1996)
Nina Saxena, Sudeep Sarkar, N. Ranganathan
Mapping and parallel implementation of Bayesian belief networks. SPDP (1996)
Minesh I. Patel, N. Ranganathan
PANTHER: a parallel neuro-systolic architecture for real-time processing. ICNN (1996)
N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar
A VLSI array architecture with dynamic frequency clocking. ICCD (1996)
Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
A tree matching chip. VLSI Design (1996)
Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan
Lossless image compression using wavelet decomposition. ICPR (1996)
N. Ranganathan, N. Bhavanishankar, Narayanan Vijaykrishnan
A dynamic frequency linear array processor for image processing. ICPR (1996)
Kameswara Rao Namuduri, N. Ranganathan, Hooman Rashedi
SVBS: a high-resolution medical image compression algorithm using slicing with variable block size segmentation. ICPR (1996)
Narayanan Vijaykrishnan, N. Ranganathan
SUBGEN: a genetic approach for subcircuit extraction. VLSI Design (1996)
S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri
A VLSI chip for image compression using variable block size segmentation. ICCD (1996)
Minesh I. Patel, N. Ranganathan
A VLSI System Architecture For Real-Time Intelligent Decision Making. ASAP (1996)
Abdel Ejnioui, N. Ranganathan
Systolic algorithms for tree pattern matching. ICCD (1995)
Mario Kovac, N. Ranganathan
JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design (1995)

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Publication Activity (10 Years)

N. Ranganathan