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Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits.
Koustav Bhattacharya
N. Ranganathan
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
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steady state
design methodology
circuit design
high level synthesis
user interface
building blocks
design process
genetic algorithm
information systems
image analysis
low cost
test cases
computer aided
power dissipation
manufacturing cell
electronic circuits