Karthikeyan Lingasubramanian

Publication Activity (10 Years)

Years Active: 2005-2020
Publications (10 Years): 7

Top Topics

Protection Scheme

Integrated Circuit

Hardware Implementation

Blind Equalization

Top Venues

Publications

Varsha Kakkara, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Karthikeyan Lingasubramanian, Senthil Murugan
A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study. PeerJ Comput. Sci. 6 (2020)
Karthi Balasubramanian, B. Yamuna, Salija P, Karthikeyan Lingasubramanian, Deepak Mishra
Effect of sign-bit-flipping trojan on turbo coded communication systems. ICDCN (2019)
A. R. Aravind, S. R. Kesavaraman, Karthi Balasubramanian, B. Yamuna, Karthikeyan Lingasubramanian
Effect of hardware Trojans on the performance of a coded communication system. ICCE (2018)
Karthikeyan Lingasubramanian, Ranveer Kumar, Nagendra Babu Gunti, Thomas Morris
Study of hardware trojans based security vulnerabilities in cyber physical systems. ICCE (2018)
Gunti Nagendra Babu, Karthikeyan Lingasubramanian
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits. Integr. 59 (2017)
Nagendra Babu Gunti, Karthikeyan Lingasubramanian
Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme. iNIS (2017)
Nagendra Babu Gunti, Karthikeyan Lingasubramanian
Neutralization of the Effect of Hardware Trojan in SCADA System Using Selectively Placed TMR. iNIS (2017)
Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian
Realizing a security aware triple modular redundancy scheme for robust integrated circuits. VLSI-SoC (2014)
Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. PATMOS (2011)
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis. Microelectron. Reliab. 51 (2) (2011)
Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja
Probabilistic Error Modeling for Nano-Domain Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Karthikeyan Lingasubramanian, Sanjukta Bhanja
An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. VLSI Design (2009)
Karthikeyan Lingasubramanian, Syed M. Alam, Sanjukta Bhanja
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis CoRR (2009)
Karthikeyan Lingasubramanian, Sanjukta Bhanja
Probabilistic maximum error modeling for unreliable logic circuits. ACM Great Lakes Symposium on VLSI (2007)
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11 (3) (2006)
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design (2005)