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Probabilistic Error Modeling for Nano-Domain Logic Circuits.
Thara Rejimon
Karthikeyan Lingasubramanian
Sanjukta Bhanja
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
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logic circuits
domain specific
pattern recognition
probabilistic model
gate array
case study
bayesian networks
image analysis
high speed
peer to peer
end to end
fault tolerant
low power
functional decomposition
nano scale