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Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating.
Karthikeyan Lingasubramanian
Andrea Calimera
Alberto Macii
Enrico Macii
Massimo Poncino
Published in:
PATMOS (2011)
Keyphrases
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power dissipation
power consumption
low power
clock gating
power reduction
digital signal processing
high speed
power saving
data center
power management
cmos technology
energy efficiency
finite state machines
design methodology
energy saving
integrated circuit
fine grained