Raghu Sastry

Publication Activity (10 Years)

Years Active: 1992-1998
Publications (10 Years): 0

Publications

Raghu Sastry, N. Ranganathan
A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47 (3) (1998)
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan
SMAC: A VLSI Architecture for Scene Matching. Real Time Imaging 4 (3) (1998)
Albert Mu, Jeff Larson, Raghu Sastry, Thomas Wicki, Winfried W. Wilcke
A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip. COMPCON (1996)
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17 (9) (1995)
Raghu Sastry, N. Ranganathan, Klinton Remedios
CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17 (8) (1995)
Raghu Sastry, N. Ranganathan
PMAC: A Polygon Matching Chip. Int. J. Pattern Recognit. Artif. Intell. 9 (2) (1995)
Raghu Sastry, N. Ranganathan
A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA (1995)
N. Ranganathan, Raghu Sastry
VLSI Architectures for Pattern Matching. Int. J. Pattern Recognit. Artif. Intell. 8 (4) (1994)
Raghu Sastry, N. Ranganathan
A Systolic Array for Approximate String Matching. ICCD (1993)
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer
SMAC: A Scene Matching Chip. ICCD (1993)
Raghu Sastry, N. Ranganathan, Horst Bunke
Hardware Algorithms for Polygon Matching. VLSI Design (1993)
Raghu Sastry, N. Ranganathan, Horst Bunke
VLSI architectures for polygon recognition. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS (1993)
R. Venkatesan, Raghu Sastry, N. Ranganathan
A VLSI architecture for hierarchical scene matching. ICPR (4) (1992)