A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip.
Albert MuJeff LarsonRaghu SastryThomas WickiWinfried W. WilckePublished in: COMPCON (1996)
Keyphrases
- traffic load
- division multiple access
- low cost
- message overhead
- medium access control
- response time
- high speed
- routing algorithm
- routing protocol
- network topology
- routing problem
- transmission delay
- qos routing
- physical design
- analog vlsi
- high density
- ad hoc networks
- routing decisions
- shortest path
- mobile ad hoc networks
- single chip
- wireless ad hoc networks
- programmable logic
- vlsi implementation
- network layer
- circuit design
- resource utilization
- low latency
- packet switching
- routing overhead