Ashok K. Murugavel

Publication Activity (10 Years)

Years Active: 2001-2004
Publications (10 Years): 0

Publications

Ashok K. Murugavel, N. Ranganathan
Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design (2004)
Ashok K. Murugavel, N. Ranganathan
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design (2004)
Ashok K. Murugavel, N. Ranganathan
Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
N. Ranganathan, Ashok K. Murugavel
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD (2003)
N. Ranganathan, Ashok K. Murugavel
A low power scheduler using game theory. CODES+ISSS (2003)
Ashok K. Murugavel, N. Ranganathan
A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design (2003)
Ashok K. Murugavel, N. Ranganathan
A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 11 (6) (2003)
Ashok K. Murugavel, N. Ranganathan
A Real Delay Switching Activity Simulator Based on Petri Net Modeling. VLSI Design (2002)
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
Least-square estimation of average power in digital CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Ashok K. Murugavel, N. Ranganathan
Petri net modeling of gate and interconnect delays for power estimation. DAC (2002)
Ashok K. Murugavel, N. Ranganathan
Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED (2002)
Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design (2001)