A VLSI chip for image compression using variable block size segmentation.

S. B. Aruru N. Ranganathan Kameswara Rao Namuduri

Published in: ICCD (1996)

Keyphrases

variable block size
high speed
image segmentation
chip design
multiscale
signal processing
motion estimation
multiresolution
object segmentation
power dissipation
multimedia
image features
computer vision
natural images
background subtraction
inter frame
block size
computational complexity