Abdel Ejnioui

Publication Activity (10 Years)

Years Active: 1995-2015
Publications (10 Years): 0

Top Topics

Sequence Diagrams

Software Requirements

Wireless Sensor

Grey Relational

Top Venues

Int. J. Wirel. Mob. Comput.

Publications

Rawad N. Al-Haddad, Rashad S. Oreifej, Ramtin Zand, Abdel Ejnioui, Ronald F. DeMara
Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics. NATW (2015)
Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero
Prioritisation of software requirements using grey relational analysis. Int. J. Comput. Appl. Technol. 47 (2/3) (2013)
Abdel Ejnioui, Carlos E. Otero, Ivica Kostanic
A stochastic approach for evaluating quality of service in wireless cellular networks. Int. J. Wirel. Mob. Comput. 6 (3) (2013)
Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi
Formalizing the design of embedded software using sequence diagrams and abstract state machines. RIIT (2013)
Rana Haber, Adrian M. Peter, Carlos E. Otero, Ivica Kostanic, Abdel Ejnioui
A support vector machine for terrain classification in on-demand deployments of wireless sensor networks. SysCon (2013)
Jeffrey A. McDougall, Luis Daniel Otero, Juan Avendano, Abdel Ejnioui
System analysis methods in emergency systems. SysCon (2013)
Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi
Engineering graphic user interfaces with protected content. SysCon (2013)
Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero
A simulation-based fuzzy multi-attribute decision making for prioritizing software requirements. RIIT (2012)
Angel R. Otero, Abdel Ejnioui, Carlos E. Otero, Gurvirender Tejay
Evaluation of Information Security Controls in Organizations by Grey Relational Analysis. Int. J. Dependable Trust. Inf. Syst. 2 (3) (2011)
Abdel Ejnioui
Runtime Adaptation in Reconfigurable System-on-Chips. ICPP Workshops (2009)
Abdel Ejnioui, Paul Bao
A parallel architecture for GFA modeling in video coding. CIT (2008)
Abdel Ejnioui, Paul Bao
A Parallel Array to Accelerate GFA Modeling in Video Coding. ERSA (2008)
Ronald F. DeMara, Yili Tseng, Abdel Ejnioui
Tiered Algorithm for Distributed Process Quiescence and Termination Detection. IEEE Trans. Parallel Distributed Syst. 18 (11) (2007)
Abdel Ejnioui
Prototyping of a Two-Phase Micropipeline on FPGAs. ERSA (2007)
Abdel Ejnioui
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. ISVLSI (2007)
Abdel Ejnioui, Paul Bao
Hardware Architectures for the Generalized Finite Automata Algorithm. ICECS (2007)
Abdel Ejnioui, Paul Bao
Hardware Acceleration of the Generalized Finite Automata Algorithm. CDES (2007)
Abdelhalim Alsharqawi, Abdel Ejnioui
Clockless Pipelining for Coarse Grain Datapaths. VLSI Design (2006)
Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
Synthesis of Pipelined SRSL Circuits. ISVLSI (2006)
Anuja Jayraj Thakkar, Abdel Ejnioui
Pipelining of double precision floating point division and square root operations. ACM Southeast Regional Conference (2006)
Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. ERSA (2006)
Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui
Pipeline synthesis of SRSL circuits. ICECS (2005)
Abdelhalim Alsharqawi, Abdel Ejnioui
SRSL pipelining of coarse-grain datapaths. ICECS (2005)
Abdel Ejnioui, Ronald F. DeMara
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. ERSA (2005)
Abdelhalim Alsharqawi, Abdel Ejnioui
Synthesis of Self-Resetting Stage Logic Pipelines. ISVLSI (2005)
Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui
Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI (2004)
Abdel Ejnioui, Abdelhalim Alsharqawi
Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI (2004)
Abdel Ejnioui, Abdelhalim Alsharqawi
Self-resetting stage logic pipelines. ACM Great Lakes Symposium on VLSI (2004)
Abdel Ejnioui, Abdelhalim Alsharqawi
Pipeline-Level Control of Self-Resetting Pipelines. DSD (2004)
Abdel Ejnioui, Abdelkader Rhiati
A Reconfigurable Memory Management Core for Java Applications. ISVLSI (2004)
Abdel Ejnioui, N. Ranganathan
Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 11 (1) (2003)
Abdel Ejnioui, N. Ranganathan
Routing on field-programmable switch matrices. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
W. Kuang, J. S. Yuan, Abdel Ejnioui
Supply Voltage Scalable System Design Using Self-Timed Circuits. ISVLSI (2003)
K. Sitaraman, N. Ranganathan, Abdel Ejnioui
A VLSI Architecture for Object Recognition Using Tree Matching. ASAP (2002)
Abdel Ejnioui, N. Ranganathan
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. Very Large Scale Integr. Syst. 9 (2) (2001)
Abdel Ejnioui, N. Ranganathan
Design Partitioning on Single-Chip Emulation Systems. VLSI Design (2000)
Abdel Ejnioui, N. Ranganathan
Routing on Switch Matrix Multi-FPGA Systems. VLSI Design (2000)
Abdel Ejnioui, N. Ranganathan
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA (1999)
Vamsi Krishna, N. Ranganathan, Abdel Ejnioui
A tree-matching chip. IEEE Trans. Very Large Scale Integr. Syst. 7 (2) (1999)
Vamsi Krishna, Abdel Ejnioui, N. Ranganathan
A tree matching chip. VLSI Design (1996)
Abdel Ejnioui, N. Ranganathan
Systolic algorithms for tree pattern matching. ICCD (1995)