Pipeline synthesis of SRSL circuits.

Rashad S. Oreifej Abdelhalim Alsharqawi Abdel Ejnioui

Published in: ICECS (2005)

Keyphrases

logic synthesis
analog circuits
high speed
analog vlsi
program synthesis
processing pipeline
digital circuits
pipeline architecture
neural network
machine learning
parallel architecture
fault diagnosis
mobile robot
image processing
delay insensitive
decision making
vlsi circuits
data mining