Franc Brglez

Publication Activity (10 Years)

Years Active: 1981-2022
Publications (10 Years): 4

Top Topics

Hamming Distance

Sequence Analysis

Stochastic Optimization Algorithm

Bipartite Graph Matching

Top Venues

Appl. Soft Comput.

Publications

Eason Li, Franc Brglez
Asymptotic Experiments with Data Structures: Bipartite Graph Matchings and Covers. CoRR (2022)
Franc Brglez
: a New Stochastic Optimization Algorithm. CoRR (2018)
Borko Boskovic, Franc Brglez, Janez Brest
Low-autocorrelation binary sequences: On improved merit factors and runtime predictions to achieve them. Appl. Soft Comput. 56 (2017)
Franc Brglez, Borko Boskovic, Janez Brest
On asymptotic complexity of the optimum Golomb ruler problem: From established stochastic methods to self-avoiding walks. CEC (2017)
Borko Boskovic, Franc Brglez, Janez Brest
Low-Autocorrelation Binary Sequences: on the Performance of Memetic-Tabu and Self-Avoiding Walk Solvers. CoRR (2014)
Franc Brglez
On Self-Avoiding Walks across n-Dimensional Dice and Combinatorial Optimization: An Introduction. CoRR (2013)
Matthias F. M. Stallmann, Franc Brglez
High-contrast algorithm behavior: observation, hypothesis, and experimental design. Experimental Computer Science (2007)
Franc Brglez, Jason A. Osborne
Performance testing of combinatorial solvers with isomorph class instances. Experimental Computer Science (2007)
Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
Effective bounding techniques for solving unate and binate covering problems. DAC (2005)
Franc Brglez, Xiao Yu Li, Matthias F. M. Stallmann
On SAT instance classes and a method for reliable performance experiments with SAT solvers. Ann. Math. Artif. Intell. 43 (1) (2005)
Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez
A Local Search SAT Solver Using an Effective Switching Strategy and an Efficient Unit Propagation. SAT (2003)
Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
Heuristics, Experimental Subjects, and Treatment Evaluation in Bigraph Crossing Minimization. ACM J. Exp. Algorithmics 6 (2001)
Franc Brglez, Hemang Lavana
A Universal Client for Distributed Networked Design and Computing. DAC (2001)
Justin E. Harlow III, Franc Brglez
Design of experiments and evaluation of BDD ordering heuristics. Int. J. Softw. Tools Technol. Transf. 3 (2) (2001)
Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan
OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. ICCD (2000)
Franc Brglez
The Scientific Method and Design and Test. IEEE Des. Test Comput. 17 (3) (2000)
Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
Heuristics and Experimental Design for Bigraph Crossing Number Minimization. ALENEX (1999)
Debabrata Ghosh, Franc Brglez
Equivalence classes of circuit mutants for experimental design. ISCAS (6) (1999)
Justin E. Harlow III, Franc Brglez
Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) (1999)
Franc Brglez, Rolf Drechsler
Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) (1999)
Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh
Evaluating iterative improvement heuristics for bigraph crossing minimization. ISCAS (6) (1999)
Hemang Lavana, Franc Brglez, Robert B. Reese
User-configurable experimental design flows on the web: the ISCAS'99 experiments. ISCAS (6) (1999)
Justin E. Harlow III, Franc Brglez
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD (1998)
Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE (1998)
Hemang Lavana, Franc Brglez
WebWise Tcl/Tk: A Safe-Tcl/Tk-based Toolkit Enhanced for the World Wide Web. Tcl/Tk Conference (1998)
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. ACM Trans. Design Autom. Electr. Syst. 3 (2) (1998)
Justin E. Harlow III, Franc Brglez
Design of experiments in BDD variable ordering: lessons learned. ICCAD (1998)
Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski
Executable Workflows: A Paradigm for Collaborative Design on the Internet. DAC (1997)
Nevin Kapur, Debabrata Ghosh, Franc Brglez
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions. ISPD (1997)
Hemang Lavana, Amit Khetawat, Franc Brglez
Internet-based workflows: a paradigm for dynamically reconfigurable desktop environments. GROUP (1997)
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
Fast true delay estimation during high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (9) (1996)
Roman Kuznar, Franc Brglez
PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists. ICCAD (1995)
Andrej Zemva, Franc Brglez
Detectable perturbations: a paradigm for technology-specific multi-fault test generation. VTS (1995)
Clay Gloster, Franc Brglez
Partial scan selection for user-specified fault coverage. EURO-DAC (1995)
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications. DAC (1994)
Andrej Zemva, Franc Brglez, Krzysztof Kozminski, Baldomir Zajc
A Functionality Fault Model: Feasibility and Applications. EDAC-ETC-EUROASIC (1994)
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
Clock Period Optimization During Resource Sharing and Assignment. DAC (1994)
Phil Allen, Franc Brglez, Hal Carter, Robert Caverly, Jerry Dillion, Albert Lo, Ron Lomax, John Oldfield, Cesar Pina, T. J. Wilkinson
Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities. SIGARCH Comput. Archit. News 22 (3) (1994)
Bernhard Rohfleisch, Franc Brglez
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. EDAC-ETC-EUROASIC (1994)
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
Provably correct high-level timing analysis without path sensitization. ICCAD (1994)
Roman Kuznar, Franc Brglez, Baldomir Zajc
Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and Interconnect. DAC (1994)
Roman Kuznar, Baldomir Zajc, Franc Brglez
A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions. EURO-DAC (1994)
Subhrajit Bhattacharya, Franc Brglez, Sujit Dey
Transformations and resynthesis for testability of RT-level control-data path specifications. IEEE Trans. Very Large Scale Integr. Syst. 1 (3) (1993)
Franc Brglez
A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema? IEEE Des. Test Comput. 10 (3) (1993)
Roman Kuznar, Franc Brglez, Krzysztof Kozminski
Cost Minimization of Partitions into Multiple Devices. DAC (1993)
Clay S. Gloster Jr., Franc Brglez
Cellular scan test generation for sequential circuits. EURO-DAC (1992)
Matthew Melton, Franc Brglez
Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults. ITC (1992)
Ulf Schlichtmann, Franc Brglez, Michael Hermann
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping. DAC (1992)
John D. Calhoun, Franc Brglez
A framework and method for hierarchical test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (1) (1992)
Sujit Dey, Franc Brglez, Gershon Kedem
Partitioning Sequential Circuits for Logic Optimization. ICCD (1991)
Sujit Dey, Franc Brglez, Gershon Kedem
Identification and Resynthesis of Pipelines in Sequential Networks. VLSI (1991)
Franc Brglez, Clay S. Gloster Jr., Gershon Kedem
Built-in self-test with weighted random pattern hardware. ICCD (1990)
Sujit Dey, Franc Brglez, Gershon Kedem
Corolla Based Circuit Partitioning and Resynthesis. DAC (1990)
Gershon Kedem, Franc Brglez, Krzysztof Kozminski
OASIS: a silicon compiler for semi-custom design. RSP (1990)
Franc Brglez, Gershon Kedem, Clay Gloster
Hardware-Based Weighted Random Pattern Generation for Boundary Scan. ITC (1989)
Clay S. Gloster Jr., Franc Brglez
Boundary scan with built-in self-test. IEEE Des. Test 6 (1) (1989)
John D. Calhoun, Franc Brglez
A Framework and Method for Hierarchical Test Generation. ITC (1989)
Clay Gloster, Franc Brglez
Boundary Scan with Cellular-Based Built-In Self-Test. ITC (1988)
Robert Lisanke, Franc Brglez, Gershon Kedem
McMAP: a fast technology mapping procedure for multi-level logic synthesis. ICCD (1988)
Franc Brglez, David Bryan, John D. Calhoun, Robert Lisanke
A modular scan-based testability system. ICCD (1988)
Michael H. Schultz, Franc Brglez
Accelerated Transition Fault Simulation. DAC (1987)
Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
Testability-Driven Random Test-Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)
Franc Brglez
A Fast Fault Grader: Analysis and Applications. ITC (1985)
Franc Brglez
Fault Coverage Tools: Case Studies. ITC (1985)
Franc Brglez, Philip Pownall, Robert Hum
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing. ITC (1984)
Franc Brglez
Digital Signal Processing Considerations in Filter-Codec Testing. ITC (1981)
G. Sakauye, Anna Lubiw, J. Royle, R. Epplett, Jeffrey Tweedale, E. S. Y. Shew, E. Attfield, Franc Brglez, Philip S. Wilcox
A set of programs for MOS design. DAC (1981)