Aart J. de Geus

Publication Activity (10 Years)

Years Active: 1984-2014
Publications (10 Years): 0

Top Topics

Recommender Systems

Information Processing

Top Venues

Publications

Aart J. de Geus
The Greatest "Tech-Onomic Push-Pull" in Human History. IEEE Des. Test 31 (2) (2014)
Aart J. de Geus
A. Richard Newton: Technologist with a Mission. IEEE Des. Test Comput. 24 (1) (2007)
Francine Bacchini, Greg Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada
Megatrends and EDA 2017. DAC (2007)
Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy
Differentiate and deliver: leveraging your partners. DAC (2005)
Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines
EDA: this is serious business. DAC (2004)
Aart J. de Geus
Electronic Industry on Fire: How to Survive and Thrive. VLSI Design (2002)
Aart J. de Geus
Slap it Together and Ship it! ISQED (2000)
Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett
Executive Perspective and Vision of the Future of EDA (Panel). DAC (1994)
Aart J. de Geus
Test: The New Value-Added Field. ITC (1994)
Aart J. de Geus
High Level Design: A Design Vision for the 90's. ICCD (1992)
Allen Dewey, Aart J. de Geus
VHDL: Toward a Unified View of Design. IEEE Des. Test Comput. 9 (2) (1992)
Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory
Testability-Driven Random Test-Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6 (6) (1987)
David Hightower, Aart J. de Geus, Patrick Fasang, Robert Griffin, Gary Leive
Computer-Aided-Design Research at the GE Microelectronics Center. IEEE Des. Test 3 (5) (1986)
Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel
Synthesis and Optimization of Multilevel Logic under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel
SOCRATES: a system for automatically synthesizing and optimizing combinational logic. DAC (1986)
Aart J. de Geus
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference. DAC (1986)
Aart J. de Geus, William W. Cohen
A Rule-Based System for Optimizing Combinational Logic. IEEE Des. Test 2 (4) (1985)
Aart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle
IDA: Interconnect delay analysis for integrated circuits. DAC (1984)