Gary D. Hachtel

Publication Activity (10 Years)

Years Active: 1982-2006
Publications (10 Years): 0

Publications

Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi
Compositional SCC Analysis for Language Emptiness. Formal Methods Syst. Des. 28 (1) (2006)
Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Chao Wang, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
Refining the SAT decision ordering for bounded model checking. DAC (2004)
Chao Wang, Gary D. Hachtel, Fabio Somenzi
Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. ICCD (2004)
Chao Wang, Gary D. Hachtel, Fabio Somenzi
The Compositional Far Side of Image Computation. ICCAD (2003)
Chao Wang, Bing Li, HoonSang Jin, Gary D. Hachtel, Fabio Somenzi
Improving Ariadneýs Bundle by Following Multiple Threads in Abstraction Refinement. ICCAD (2003)
Chao Wang, Gary D. Hachtel
Sharp Disjunctive Decomposition for Language Emptiness Checking. FMCAD (2002)
Chao Wang, Roderick Bloem, Gary D. Hachtel, Kavita Ravi, Fabio Somenzi
Divide and Compose: SCC Refinement for Language Emptiness. CONCUR (2001)
Jae-Young Jang, In-Ho Moon, Gary D. Hachtel
Iterative Abstraction-Based CTL Model Checking. DATE (2000)
In-Ho Moon, Gary D. Hachtel, Fabio Somenzi
Border-Block Triangular Form and Conjunction Schedule in Image Computation. FMCAD (2000)
Abelardo Pardo, Gary D. Hachtel
Incremental CTL Model Checking Using BDD Subsetting. DAC (1998)
In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
Approximate reachability don't cares for CTL model checking. ICCAD (1998)
R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
Algebraic Decision Diagrams and Their Applications. Formal Methods Syst. Des. 10 (2/3) (1997)
R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (10) (1997)
Abelardo Pardo, Gary D. Hachtel
Automatic Abstraction Techniques for Propositional µ-calculus Model Checking. CAV (1997)
Gary D. Hachtel, Fabio Somenzi
A Symbolic Algorithms for Maximum Flow in 0-1 Networks. Formal Methods Syst. Des. 10 (2/3) (1997)
Woohyuk Lee, Abelardo Pardo, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi
Tearing based automatic abstraction for CTL model checking. ICCAD (1996)
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
VIS: A System for Verification and Synthesis. CAV (1996)
Kavita Ravi, Abelardo Pardo, Gary D. Hachtel, Fabio Somenzi
Modular Verification of Multipliers. FMCAD (1996)
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa
VIS. FMCAD (1996)
Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
Symbolic computation of logic implications for technology-dependent low-power synthesis. ISLPED (1996)
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
Markovian analysis of large finite state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
Algorithms for approximate FSM traversal based on state space decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
CMOS dynamic power estimation based on collapsible current source transistor modeling. ISLPD (1995)
Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
Computing the Maximum Power Cycles of a Sequential Circuit. DAC (1995)
Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
Extended BDDs: Trading off Canonicity for Structure in Verification Algorithms. Formal Methods Syst. Des. 4 (2) (1994)
Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. ICCD (1994)
Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
Timing Analysis of Combinational Circuits using ADD's. EDAC-ETC-EUROASIC (1994)
Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
A State Space Decomposition Algorithm for Approximate FSM Traversal. EDAC-ETC-EUROASIC (1994)
R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
A symbolic method to reduce power consumption of circuits containing false paths. ICCAD (1994)
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine. EDAC-ETC-EUROASIC (1994)
Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
Probabilistic Analysis of Large Finite State Machines. DAC (1994)
Gary D. Hachtel, Mariano Hermida de la Rica, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
Re-encoding sequential circuits to reduce power dissipation. ICCAD (1994)
R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
An ADD-based algorithm for shortest path back-tracing of large graphs. Great Lakes Symposium on VLSI (1994)
June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi, Reily M. Jacoby
Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (2) (1994)
Gary D. Hachtel, Fabio Somenzi
A symbolic algorithm for maximum flow in 0-1 networks. ICCAD (1993)
Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi
Algorithms for Approximate FSM Traversal. DAC (1993)
Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (7) (1993)
R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
Algebraic decision diagrams and their applications. ICCAD (1993)
Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC (1992)
Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison
On properties of algebraic transformations and the synthesis of multifault-irredundant circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (3) (1992)
Xuejun Du, Gary D. Hachtel, Bill Lin, A. Richard Newton
MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (1) (1991)
Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
Fast Sequential ATPG Based on Implicit State Enumeration. ITC (1991)
Seon-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
Variable Ordering and Selection for FSM Traversal. ICCAD (1991)
Gary D. Hachtel, June-Kyung Rho, Fabio Somenzi, Reily M. Jacoby
Exact and heuristic algorithms for the minimization of incompletely specified state machines. EURO-DAC (1991)
June-Kyung Rho, Gary D. Hachtel, Fabio Somenzi
Don't Care Sequences and the Optimization of Interacting Finite State Machines. ICCAD (1991)
Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi
Redundancy Identification and Removal Based on Implicit State Enumeration. ICCD (1991)
Seh-Woong Jeong, Bernard Plessier, Gary D. Hachtel, Fabio Somenzi
Extended BDD's: Trading off Canonicity for Structure in Verification Algorithms. ICCAD (1991)
Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi
ATPG Aspects of FSM Verification. ICCAD (1990)
Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli
Multilevel logic synthesis. Proc. IEEE 78 (2) (1990)
Hyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi
Results on the Interface between Formal Verification and ATPG. CAV (DIMACS/AMS volume) (1990)
Reily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel
New ATPG techniques for logic optimization. ICCAD (1989)
Gary D. Hachtel, Christopher R. Morrison
Linear complexity algorithms for hierarchical routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (1) (1989)
Gary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison
On properties of algebraic transformation and the multifault testability of multilevel logic. ICCAD (1989)
Glenn Colón-Bonet, Eric M. Schwarz, D. G. Bostick, Gary D. Hachtel, Michael R. Lightner
On optimal extraction of combinational logic and don't care sets from hardware description languages. ICCAD (1989)
Gary D. Hachtel, Reily M. Jacoby, P. Moceyunas, Christopher R. Morrison
Performance enhancements in BOLD using 'implications'. ICCAD (1988)
Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (6) (1988)
Gary D. Hachtel, Reily M. Jacoby
Verification algorithms for VLSI synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (5) (1988)
Hyunwoo Cho, Gary D. Hachtel, M. Nash, L. Setiono
BEATNP: a tool for partitioning Boolean networks. ICCAD (1988)
Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel
Synthesis and Optimization of Multilevel Logic under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)
David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel
SOCRATES: a system for automatically synthesizing and optimizing combinational logic. DAC (1986)
Michael R. Lightner, Gary D. Hachtel, Richard H. Byrd, Michel Heydemann
A Theory and Algorithmic Frame for Switch Level Simulation. IMACS European Simulation Meeting (1984)
Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
An Algorithm for Optimal PLA Folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 (2) (1982)
Gary D. Hachtel, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
Techniques for programmable logic array folding. DAC (1982)
Michael R. Lightner, Gary D. Hachtel
Implication algorithms for MOS switch level functional macromodeling implication and testing. DAC (1982)