Carl Pixley

Publication Activity (10 Years)

Years Active: 1988-2009
Publications (10 Years): 0

Publications

Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley
Solver technology for system-level to RTL equivalence checking. DATE (2009)
Carl Pixley
Practical Considerations Concerning HL-to -RT Equivalence Checking. Haifa Verification Conference (2008)
Alfred Kölbl, Jerry R. Burch, Carl Pixley
Memory Modeling in ESL-RTL Equivalence Checking. DAC (2007)
In-Ho Moon, Per Bjesse, Carl Pixley
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. DATE (2007)
Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley
Panel: Assertion-Based Verification -What's the Big Deal? HLDVT (2006)
In-Ho Moon, Per Bjesse, Carl Pixley
Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. HLDVT (2006)
Sandeep K. Shukla, Carl Pixley, Gary Smith
Guest Editors' Introduction: The True State of the Art of ESL Design. IEEE Des. Test Comput. 23 (5) (2006)
Alfred Kölbl, Carl Pixley
Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation. Int. J. Parallel Program. 33 (6) (2005)
Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin
Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (3) (2004)
Carl Pixley, Sharad Malik
Guest Editors' Introduction: Exploring Synergies for Design Verification. IEEE Des. Test Comput. 21 (6) (2004)
In-Ho Moon, Carl Pixley
Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. FMCAD (2004)
Carl Pixley, D. Meyers, S. McMaster, A. Chittor
Designers want proofs - but show me the money. MEMOCODE (2004)
Carl Pixley, Juan Antonio Carballo
Panel Summaries. IEEE Des. Test Comput. 20 (4) (2003)
Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
Formal verification - prove it or pitch it. DAC (2003)
Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8 (2) (2003)
Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin
A Framework for Constrained Functional Verification. ICCAD (2003)
Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
Constraint synthesis for environment modeling in functional verification. DAC (2003)
Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD (2002)
In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley
Simplifying Circuits for Formal Verification Using Parametric Representation. FMCAD (2002)
Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley
Simplifying Constraint Solving in Random Simulation Generation. IWLS (2002)
Shuvendu K. Lahiri, Carl Pixley, Ken Albin
microprocessor core. HLDVT (2001)
Noel R. Strader, Gérard Memmi, Carl Pixley
Application of Formal Verification to Design Creation and Implementation. ISQED (2001)
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (2) (2001)
Carl Pixley
Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. IEEE Des. Test Comput. 18 (4) (2001)
Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
Automatic Vector Generation Using Constraints and Biasing. J. Electron. Test. 16 (1-2) (2000)
Jaehong Park, Carl Pixley, Michael Burns, Hyunwoo Cho
An Efficient Logic Equivalence Checker for Industrial Circuits. J. Electron. Test. 16 (1-2) (2000)
Carl Pixley, Kurt Shultz, Jun Yuan
Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. PDPTA (1999)
Carl Pixley, Vigyan Singhal
Model Checking: A Hardware Design Perspective. Int. J. Softw. Tools Technol. Transf. 2 (3) (1999)
Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz
Modeling design constraints and biasing in simulation using BDDs. ICCAD (1999)
Jainendra Kumar, Carl Pixley
Logic and Functional Verification in a Commercial Semiconductor Environment. ACSD (1998)
Matt Kaufmann, Andrew Martin, Carl Pixley
Design Constraints in Symbolic Model Checking. CAV (1998)
In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley
Approximate reachability don't cares for CTL model checking. ICCAD (1998)
Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley
Formal Verification of FIRE: A Case Study. DAC (1997)
Matt Kaufmann, Carl Pixley
Intertwined Development and Formal Verification of a 60x Bus Model. ICCD (1997)
Carl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen
Commercial Design Verification: Methodology and Tools. ITC (1996)
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
The Validity of Retiming Sequential Circuits. DAC (1995)
Vigyan Singhal, Robert K. Brayton, Carl Pixley
Power-Up Delay for Retiming Digital Circuits. ISCAS (1995)
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton
Exploiting power-up delay for sequential optimization. EURO-DAC (1995)
Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
Exact calculation of synchronizing sequences based on binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton
Multi-level synthesis for safe replaceability. ICCAD (1994)
Vigyan Singhal, Carl Pixley
The Verifiacation Problem for Safe Replaceability. CAV (1994)
June-Kyung Rho, Fabio Somenzi, Carl Pixley
Minimum Length Synchronizing Sequences of Finite State Machine. DAC (1993)
Hyunwoo Cho, Seh-Woong Jeong, Fabio Somenzi, Carl Pixley
Synchronizing sequences and symbolic traversal techniques in test generation. J. Electron. Test. 4 (1) (1993)
Carl Pixley
A theory and implementation of sequential hardware equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (12) (1992)
Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel
Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. DAC (1992)
Carl Pixley, Gary Beihl
Calculating Resetability and Reset Sequences. ICCAD (1991)
Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes
Automatic Derivation of FSM Specification to Implementation Encoding. ICCD (1991)
Carl Pixley
A Computation Theory and Implementation of Sequential Hardware Equivalence. CAV (DIMACS/AMS volume) (1990)
Carl Pixley
Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. CAV (1990)
Carl Pixley
An Incremental Garbage Collection Algorithm for Multi-Mutator Systems. Distributed Comput. 3 (1) (1988)