Jerry R. Burch

Publication Activity (10 Years)

Years Active: 1985-2007
Publications (10 Years): 0

Publications

Alfred Kölbl, Jerry R. Burch, Carl Pixley
Memory Modeling in ESL-RTL Equivalence Checking. DAC (2007)
Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
Refinement preserving approximations for the design and verification of heterogeneous systems. Formal Methods Syst. Des. 31 (1) (2007)
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC (2005)
Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli
Conservative approximations for heterogeneous design. EMSOFT (2004)
Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
Using Multiple Levels of Abstractions in Embedded Software Design. EMSOFT (2001)
Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. ACSD (2001)
Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
Constraints specification at higher levels of abstraction. HLDVT (2001)
Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
Sibling-substitution-based BDD minimization using don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (1) (2000)
Jerry R. Burch, Vigyan Singhal
Robust latch mapping for combinational equivalence checking. ICCAD (1998)
Jerry R. Burch, Vigyan Singhal
Tight integration of combinational verification methods. ICCAD (1998)
Peter A. Beerel, Jerry R. Burch, Teresa H. Meng
Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods Syst. Des. 13 (1) (1998)
Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan
Safe BDD Minimization Using Don't Cares. DAC (1997)
Phillip J. Windley, Jerry R. Burch
Mechanically Checking a Lemma Used in an Automatic Verification Tool. FMCAD (1996)
Jerry R. Burch
Techniques for Verifying Superscalar Microprocessors. DAC (1996)
Robert B. Jones, David L. Dill, Jerry R. Burch
Efficient validity checking for processor verification. ICCAD (1995)
Jerry R. Burch, David L. Dill
Automatic verification of Pipelined Microprocessor Control. CAV (1994)
Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill
Symbolic model checking for sequential circuit verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (4) (1994)
Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng
Sufficient conditions for correct gate-level speed-independent circuits. ASYNC (1994)
Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng
Efficient verification of determinate speed-independent circuits. ICCAD (1993)
Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli
Modeling hierarchical combinational circuits. ICCAD (1993)
Jerry R. Burch, David E. Long
Efficient Boolean function matching. ICCAD (1992)
Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
Symbolic Model Checking: 10^20 States and Beyond Inf. Comput. 98 (2) (1992)
Jerry R. Burch
Delay Models for Verifying Speed-Dependent Asynchronous Circuits. ICCD (1992)
Jerry R. Burch, Edmund M. Clarke, David E. Long
Symbolic Model Checking with Partitioned Transistion Relations. VLSI (1991)
Jerry R. Burch
Using BDDs to Verify Multipliers. DAC (1991)
Jerry R. Burch, Edmund M. Clarke, David E. Long
Representing Circuits More Efficiently in Symbolic Model Checking. DAC (1991)
Jerry R. Burch
Verifying Liveness Properties by Verifying Safety Properties. CAV (DIMACS/AMS volume) (1990)
Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill
Sequential Circuit Verification Using Symbolic Model Checking. DAC (1990)
Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang
Symbolic Model Checking: 10^20 States and Beyond LICS (1990)
Jerry R. Burch
Verifying Liveness Properties by Verifying Safety Properties. CAV (1990)
Jerry R. Burch
Combining CTL, Trace Theory and Timing Models. Automatic Verification Methods for Finite State Systems (1989)
Jerry R. Burch
Modeling timing assumptions with trace theory. ICCD (1989)
Alain J. Martin, Jerry R. Burch
Fair Mutual Exclusion with Unfair P and V Operations. Inf. Process. Lett. 21 (2) (1985)